Infineon Unveils 12 kW PSU Reference Design for AI Data Centers

Infineon has released a 12 kW power supply unit (PSU) reference design for AI data centers and server platforms. The design combines silicon, silicon carbide, and gallium nitride devices to reach high conversion efficiency and power density, and it targets engineers building next-generation rack power architectures.

The 12 kW PSU reference design. Image used courtesy of Infineon

12 kW Reference Design

In the reference design, the AC/DC front end implements a three-level flying capacitor interleaved PFC topology. Infineon specifies peak efficiency above 99.0% and notes that the approach cuts magnetic component volume while operating on a wide bandgap platform. Infineon attributes the switching performance and thermal headroom to the CoolSiC devices used in this stage.

For isolation and voltage transformation, the PSU uses a full-bridge LLC resonant converter. The company reports peak efficiency above 98.5%, achieved with two planar high-frequency transformers and GaN switches from the CoolGaN portfolio. Planar magnetics and GaN collectively support high switching frequency and tighter profiles to raise volumetric density. Infineon measures the resulting power density at up to 113 W/in^3 for the overall design.

To handle ride-through requirements without a large electrolytic bulk, the design also integrates a bidirectional energy buffer into the PSU’s main topology. According to Infineon, this converter satisfies hold-up time specifications while materially reducing required capacitance. The energy buffer also performs grid shaping, which the company characterizes as limiting both the magnitude and rate of change of input power during transients to improve system reliability.

Bidirectional Energy Buffers and Hold-Up Time

Hold-up time is when a PSU must maintain a regulated output after an AC input dropout. While conventional solutions store energy in large bulk capacitors on the high-voltage DC bus, at multi-kilowatt ratings, these capacitors dominate volume, limit power density, and create inrush and thermal challenges.

A bidirectional energy buffer resolves this issue by inserting a controlled storage stage between the DC bus and an energy reservoir. During normal operation, the buffer charges the storage element (e.g., film capacitor bank or supercapacitor) to a target voltage while maintaining bus regulation. When the input dips, the buffer reverses power flow to inject energy back to the bus to sustain downstream converters through the required hold-up interval.

A bidirectional power supply. Image used courtesy of Matsusada

Because the buffer controls charge and discharge actively, designers can reduce electrolytic capacitance substantially while shaping the input current profile. Limiting the slew rate of power drawn from the mains during load steps reduces grid stress and eases PFC component sizing.

Control strategies typically monitor bus voltage, storage state of charge, and thermal limits, and they schedule charge windows to avoid stacking peaks with load transients. In this context, efficiency depends on minimizing conversion stages and switching losses, and high-frequency, soft-switched topologies can help achieve low conduction loss in both directions. Otherwise, reliability considerations include fault-tolerant gating, thermal derating at elevated ambient, voltage balancing across series storage cells, and protection for reverse energy flow paths.

In high-power applications, such an architecture translates into slimmer front ends, higher power density, and improved transient stability. The trade-offs, however, include buffer converter complexity, controls integration, and validation across worst-case line and load dynamics.

12 kW Reference for Rack-Level Roadmaps

At a time when accelerator racks are driving rising current demands and tighter thermal budgets, Infineon’s reference can be a wayfinder for high-power front ends and isolated stages. The reference design is currently available as a reference board.