Navitas Reveals 3300 V and 2300 V SiC Product Portfolio

Navitas Semiconductor is providing samples of its 3300 V and 2300 V ultra-high-voltage (UHV) silicon carbide devices, available in power module, discrete, and known-good-die (KGD) formats. The portfolio is based on the company’s latest GeneSiC fourth-generation trench-assisted planar (TAP) MOSFET platform, which reduces voltage stress and strengthens blocking performance compared with both trench and traditional planar SiC MOSFETs.

The G+ SiC MOSFET products. Image used courtesy of Navitas

The 3300 V and 2300 V TAP-Based Portfolio

Navitas’ 3300 V and 2300 V MOSFETs use the company’s TAP architecture to implement a controlled, multi-step electric-field distribution profile.

Navitas complements its device architecture with a portfolio of packaging formats tuned for UHV reliability. The SiCPAK G+ module family uses epoxy-resin potting rather than silicone gel, achieving more than 60% improvement in power-cycling lifetime and a greater than 10x increase in thermal-shock robustness. The modules incorporate aluminum nitride DBC substrates to support high thermal conductivity and include enhanced press-fit pins that double the current capacity per pin.

Current spreading in different MOSFET technologies. Image used courtesy of Navitas

Navitas also ensures device reliability through its AEC-Plus qualification methodology, which builds on AEC-Q101 by adding longer high-temperature, high-voltage testing (HTRB, HTGB, HTGB-R), dynamic reverse-bias and gate-switching tests, HV-THB for modules, and HV-H3TRB for discrete and bare-die products.

Deeper on the TAP Architecture

When constructing TAP SiC MOSFETs, Navitas starts with the traditional planar approach, where the current path forms along the top surface of the SiC wafer. This planar geometry simplifies fabrication by avoiding deep, high-aspect-ratio trench etching and tends to support higher manufacturing yield. However, conventional planar structures often encounter electric-field crowding at junction edges, resulting in stress on the gate oxide and reduced avalanche robustness at high blocking voltages.

The TAP structures approach these limitations through field-management trenches in the source region that produce a multi-step electric-field profile that smooths transitions between high- and low-field regions in the device. By moderating field peaks near cell corners and gate edges, the architecture can reduce oxide stress and stabilize long-term threshold-voltage behavior.

TAP versus traditional planar devices. Image used courtesy of Navitas

Current spreading also improves under the TAP geometry. The stepped field profile helps distribute current more uniformly across the cell, reduces localized heating, and lowers effective on-resistance at high temperatures. This approach mitigates the RDS(on) increase that typically accompanies high-temperature operation in wide-bandgap MOSFETs. Therefore, the architecture supports lower conduction losses and consistent performance over a broader thermal range.

Switching behavior benefits from the same structural principles. Reduced parasitic capacitances and controlled field gradients unlock lower switching energy under high-dV/dt conditions.

While pure trench MOSFETs can deliver very low specific on-resistance, they face gate-oxide reliability constraints because of field concentration at vertical trench corners. TAP designs avoid this trade-off by retaining planar gate geometry while still using shallow trenches to guide the field.

Toward Higher-Voltage Architectures

Navitas’ 3300 V and 2300 V SiC devices may give system designers a platform that sidesteps many of the reliability constraints that typically shape UHV power-electronic architectures. Sample devices are immediately available in module, discrete, and KGD formats through Navitas sales channels.