Control Method for a Reverse Conducting IGBTNovember 28, 2016 by Daniel Domes
This article discusses the advantages of combining the functionality of an IGBT and diode resulting in a reverse conducting IGBT (RC-IGBT).
When IGBT and diode functionality is combined into a single piece of silicon, a reverse conducting IGBT (RC-IGBT) is created. This allows a standard IGBT/diode-module to be built on a single silicon chip. This results in enhanced current carrying capability without increasing the footprint of the module and – depending on the device technology – allowing the diode´s electrical performance to be influenced by the control state of the IGBT gate. However, in order to manage the losses in the combined RC-IGBT, special control approaches need to be considered.
Reverse conducting IGBTs can be built by partially interrupting the p-doped collector area with n-doped regions. This creates the diode functionality, yet there remains sufficient area for the IGBT to inject minority carriers into the drift region for low forward voltage (VCE(sat)).
With this approach, the diode functionality is dependent on the state of the gate control. Devices of this type are designed for hard switching applications, and are known as Reverse Conducting IGBTs with Diode Control (RCDC-IGBT).
Loss Optimal RCDC-IGBT Performance
The RCDC-IGBT gate state has a significant impact on the forward characteristics of the diode. From the static loss perspective, in diode conduction mode the gate needs to be turned off. The lowest VF can be achieved when VGE=-15 V, this is a little higher when VGE=0 V. Since VF corresponds to the carrier density inside the chip, for the lowest dynamic losses and thus lowest Qrr, VF should be selected to be a high value.
Deciding how to drive the gate in diode conduction mode will depend on the pulse frequency of the application and the ability to desaturate the diode prior to it turning off.
Special Gate Drive Aspects
A gate driver for low loss RCDC-IGBT operation needs to be able to:
- detect the diode conduction mode and prevent turn-on of the RCDC-IGBT gate
- desaturate the RCDC-IGBT diode by driving VGE to 15 V prior to diode turn off
- drive VGE to 0 V in diode conduction mode in the case of a typical 6.5 kV inverter pulse frequency and limited diode desaturation time
- detect a load current zero-crossing in diode mode and turn on the RCDC-IGBT gate for smooth current transition from the diode to the IGBT of the same switch
- detect the load current zero-crossing in IGBT mode and turn off the RCDC-IGBT gate for low loss diode operation
Detect the Diode Conduction Mode
In a classic inverter, a forward conducting IGBT is turned off at the start of the interlock time period. For the opposite diode, this means that first, the blocking voltage decreases and then the current starts to rise. Once the interlock time period is over, the antiparallel IGBT gate of the diode is turned on. For an RCDC-IGBT, the turn-on of the conducting diode´s antiparallel IGBT needs to be prevented by the gate driver logic.
It is recommended to monitor the VCE of the switch before executing the turn-on command from the control side. In this scenario, the voltage across the diode switch is low before the interlock time ends, clearly indicating that the diode is conducting.
For diode desaturation purposes, the interlock time is calculated for each gate driver individually. Consequently, the high and low side gate driver input signals will change at the same time. Falling edges of the control signal are executed immediately, turning off the LS-IGBTs gate. The IGBT turns off normally and the voltage across the high side switch decreases. A voltage detector checks whether the VCE of the high side switch drops below a defined threshold (displayed as “VCE low”). In this case, the high side switch will go into diode conduction mode and the gate (VGE) is switched from -15 V to 0 V as soon as the detector output “VCE low” changes.
The high voltage detector is a simple frequency-compensated voltage divider. In high voltage applications, this circuit is often present in the gate driver stage for desaturation detection purposes and adds no additional parts to the Bill of Material (BOM).
Detecting the diode conduction state and keeping the corresponding switch gate in the off-state ensures a high carrier density inside the device thus maintaining low VF-values. However, for dynamic loss reduction this condition is not desired as high carrier density causes high Qrr and hence high IGBT turn on and diode turn off losses.
If the diode switch gate is turned on before the diode is turned off, the operation point is shifted from a low to a high VF output curve and the diode carrier concentration is reduced with a strong effect on the dynamic losses. Typical desaturation time for a 6.5 kV RCDC-IGBT is 20 to 100 µs.
For practical implementation, the driver needs to accurately predict the point in time at which the diode turns off. This corresponds to the opposite IGBT turning on, which (based on the signal definitions) is executed after the IGBT switch control signal changes from low to high and the interlock time, tinterlock, is over.
This approach is illustrated in Figure 4. The high side switch diode conduction state was detected and the gate switched to VGE=0. Now, the high side and low side gate input signals change synchronously. The low side gate driver counts the interlock time and when it is over, turns on the low side IGBT.
The diodes switch gate driver creates the desaturation pulse by driving VGE to 15 V. No active switching in the half-bridge occurs until the interlock timer is over. The gate driver of the diode switch remains with VGE at 15 V for the desaturation time (tdesat). The duration of tdesat is shorter than, tinterlock, since the remaining locking time, tlock, must be added. The locking time should be kept small to prevent the diode saturating again, reducing the effect of the desaturation. A typical value of tlock for a 6.5 kV RCDC IGBT is 0.5 µs.
With this approach, the diode desaturation duration corresponds to the maximum interlock time tolerated by the application. A long interlock time ensures best device performance but decreases the dynamic response of the system. Using a very small gate resistor applies the shortest time constants for the desaturation pulse and gives the best desaturation result. In Figure 2 references this resistor as RGD, whereas the nominal gate resistors are named RGI(on) and RGI(off).
Considering a practical 6.5 kV traction inverter system with a frequency of several hundred Hertz and maximum interlock time of 20µs, the RCDC-IGBT performs best if the gate runs at 0 V in diode conduction mode. In this case, the static diode losses are slightly higher than with operation at VGE=-15 V. Total losses are minimized as Qrr is lower than with VGE=-15 V diode operation. For other frequencies and longer desaturation times, the optimal operation timing will be different.
Load Current Zero Crossing Approach: Diode to IGBT
If, in a classical inverter approach, a diode is conducting then the load current can change polarity as the antiparallel IGBT is normally turned on via the gate. For an RCDC-IGBT, this situation must be detected and the gate turned on immediately to avoid interrupting the load current.
If a PN-diode conducts and the current decreases to zero, the diode remains flooded with carriers allowing the load current to reverse direction even though the antiparallel IGBT gate is not turned on. In Figure 5a, the load current (IL) changes direction at t4 but, as IC(HS), still flows through the diode. The high side IGBT gate remains in an off state, as its control signal is low. As soon as the carriers in the diode are depleted by the load current, the voltage across the diode reverses at time t5. The load current di/dt is small compared to di/dt in a hard switching event.
The gate driver must check for positive VCE while the diode is conducting. As soon as VCE becomes positive, the gate is immediately turned on. The detection circuit must be able to react to low positive VCE voltages, to avoid the output voltage change becoming unnecessarily high. In Figure 5a, at time t5 this effect is exaggerated. It is advised to use a classical desaturation detection circuit with a high voltage diode chain, a current source and a comparator.
Figure 6 shows the load current commutation from the diode to the IGBT by means of RCDC IGBTs in an H-bridge configuration. The gate driver circuit detects the small increase in VCE (inset) and turns on the RCDC-IGBTs gate. The load current changes polarity without interruption or excessive voltage distortion.
Load Current Zero Crossing Approach: IGBT to Diode
As well as the transition of the load current from the diode to the IGBT, the current can also change its direction to flowing from the IGBT into the antiparallel diode. This does not risk interrupting the load current as the gate remains in an on state and the diode sinks the current. If VGE remained at 15 V, VF would be unnecessarily high and thus the static losses increase until the next control command is received. It is recommended to use the proposed desaturation circuit again, detecting a small VCE voltage across the RCDC-IGBT. Since VF is initially high, the voltage difference in VCE from IGBT to diode conduction also becomes high and can easily be detected.
Figure 2 shows the complete RCDC-IGBT gate driver control scheme. The state machine is able to handle all basic RCDC-IGBT gate drive requirements including diode conduction mode detection, diode desaturation, load current zero-crossing from diode to IGBT and vice versa.
Figure 7 shows the gate driver used. If IGBT switching is required, the gate resistors RGI(on) and RGI(off) are used. If minimum time constant switching is required to desaturate the diode, a comparatively small RGD is used. The advanced H-bridge concept allows VGE to be driven to 0 V when the diode is conducting.
In high voltage IGBT gate drivers, a high voltage divider is commonly used for desaturation detection. The RCDC-IGBT gate driver has a desaturation circuit consisting of a high voltage diode chain, comparator and current source. Logically, three binary input signals “ctrl”, “VCE” and “HV desat” are processed by the state machine.
About the Author
Daniel Domes works as a Senior Staff Engineer at Infineon Technologies, Germany. He graduated in electrical engineering in 2003. While working as a research associate at Chemnitz University of Technology, he dealt with converter control and the use of SiC power devices in various converter topologies. In 2009 he received his doctorate. Since 2008, he has been working at Infineon Technologies AG with a focus on innovative concepts for the application of power semiconductor chips.