A Comparison of FinFET Configurations

Since the invention in 1958 of the integrated circuit, engineers and researchers worldwide have looked for ways to increase their speed and performance.

The result has been the growth of the number of devices per integrated circuit or chip following the well-known Moore’s Law, an empirical relationship formulated by Gordon E. Moore (G.E. Moore: Cramming More Components onto Integrated Circuits. Electronics, Vol 38, Number 8,1965). He stated that the number of transistors built into each chip increased at a rate of roughly a factor of two per year and predicted that this rate could continue or grow for the next ten years, at least.

Since the 70s, the number of elements per integrated circuit has doubled every two years. However, it is fundamental to maintain integrated circuit size within practical and affordable limits.

The rise in the number of transistors per chip has been achieved by increasing the chip’s surface area and decreasing each transistor’s size. However, the decrease in transistor size is the main contributor to a more significant capacity per chip.

The semiconductor industry has evolved extraordinarily, especially regarding MOSFET (metal oxide semiconductor field effect transistor) technology. Still, as device size decreases, researchers face increasingly difficult technological barriers related to the fabrication of the device itself and its electrical characteristics.

The conventional CMOS arrangement is reaching its scaling limit. Enormously scaled MOSFETs have very narrow channel lengths. The drain potential influences the channel’s electrostatics, causing the gate to lose control over it to such an extent that it cannot turn off the channel entirely and increases the Ioff between drain and source.

Increasing the gate-channel capacitance by using thinner gate oxides and high-k dielectric materials alleviates the drawback. Therefore, there is a constant dedication to finding new devices with properties that fit current and future requirements. Among the many proposed, the so-called multi-gate transistors, such as FinFETs, stand out.

In this article, we look at different device configurations of MOSFETs and FinFETs and their evolution. We also see how the 3D configuration allows for more transistors per integrated circuit.

 

Planar vs. Three-Dimensional (3D)

Planar MOSFETs (Figure 1) lose control of leakage current as Lg scales downward.

The answer is utilizing the third dimension.

MOSFET transistors evolved from planar, single-gate devices into multi-gate 3D units to increase the current drive and mitigate short-channel effects.

Using 3D also reduces the area of the transistor. Occupying the third dimension allows shrinking each transistor area to get the same volume, resulting in more transistors in the same total size.

 

Figure 1. Planar MOSFET

 

In a planar design, the gate controls in only one direction. In a 3D design, the gate wraps around the fin, providing control in two or three directions (Figure 2). Then, the gate regains control of the thin body.

 

Figure 2. FinFET

 

Furthermore, moving from planar to 3-D reduces the sub-threshold slope and the Ioff current. The volume will increase, and the leakage current will be less than in a planar design.

 

Double-Gate vs. Tri-Gate FinFETs

Double-gate implies a single gate electrode facing two opposite sides of the fin (front and back gates).

Double-gate FinFETs have a dielectric layer – called a hard mask – above the fin to inhibit the electric field. The dielectric layer prevents parasitic inversion channels at the top corners. The gate control is from the sides and not from the top (Figure 3).

 

Figure 3. Double-gate FinFET

 

Tri-gate denotes a single gate electrode folded over three sides of the fin. There is no inhibition of the electric field above the fin in the tri-gate, and the gate exerts control from the three sides (Figure 4).

 

Figure 4. Tri-gate FinFET

 

The third gate adds to process complexity, has benefits – reduced gate-source capacitance and extra transistor width – and drawbacks –  increased parasitic resistance.

 

π-gate and Ω-gate devices

The π-gate (Figure 5) and Ω-gate (Figure 6) devices are formed by lengthening the sidewall sections of the three-gate FinFET underneath the channel. This arrangement increases the effective number of gates from three to four, improving electrostatic integrity.

 

Figure 5. π-gate FinFET

Figure 6. Ω-gate FinFET

 

Shorted-Gate (SG) vs. Independent Gate (IG)

The shorted-gate FET (SG FinFET) has the front and back gates short-circuited and only one terminal. It is a three-terminal device: source, drain, and gate. There is no external control of the threshold voltage (Vth).

The independent-gate FET (IG FinFET) is a four-terminal device (Figure 7). This arrangement is a double-gate device with the gate electrodes isolated by a masked etch to allow for separate biasing (separate channel control).

 

Figure 7. Independent-gate FinFET

 

One gate is used for switching, and the other controls the threshold voltage: the Vth of one gate is modulated by the other gate’s bias.

The individual control of the electrodes reduces the leakage current. The IG FinFET requires more area than the SG FinFET.

 

Silicon-On-Insulator (SOI) vs. Bulk-Si FinFETS

FinFETs have been fabricated on silicon-on-insulator (SOI) wafers and conventional bulk wafers.

The SOI configuration has an insulation layer (BOX or Buried OXide layer) between the fin and the silicon substrate (Figure 8).

 

Figure 8. SOI FinFET

 

The bulk FinFET employs bulk silicon instead of an SOI wafer – the fin connects to the silicon substrate (Figure 9).

 

Figure 9. Bulk FinFET

 

Initial research was done in an SOI substrate with an oxide layer because it is easier to define and control the fin.

In 1990, Hisamoto et al. published the first paper on FinFET (A fully DEpleted Lean-channel TrAnsistor (DELTA) – a novel vertical ultra-thin SOI MOSFET). They used an SOI substrate with an oxide layer and patterned the silicon on top with a fin’s shape (Figure 10).

 

Figure 10. DELTA MOSFET. Image: D. Hisamoto, et al., 1990

 

Intel announced the use of the bulk configuration in 2012 (22 nm technology) (Figure 11).

 

Figure 11. Intel’s FinFET. Image: Intel Corp.

 

Some basic features are:

SOI

• More expensive
• Low heat dissipation through the oxide layer. Heat dissipation may be an issue
• No parasitic BJT
• Reduced parasitic capacitances
• Enhanced current drive

 

Bulk

• Lower cost
• Better heat dissipation through the silicon substrate because it is a reasonable conductor of heat. Silicon has a thermal conductivity higher than that of oxide
• Parasitic BJT.