Selecting the Right SiC MOSFET for Efficient Zero-Voltage Switching

Article co-authored by Thomas Lehmeier, Yan Zhou, and Martin März, Institute of Power Electronics, Friedrich-Alexander-Universität Erlangen-Nürnberg.

This article is published by EEPower as part of an exclusive digital content partnership with Bodo’s Power Systems.

Zero-voltage switching enables efficient power conversion at high frequencies. While ZVS significantly reduces switching losses, some residual losses still remain. Researchers from FAU Erlangen-Nürnberg benchmarked 1200 V SiC MOSFETs through calorimetric loss measurements at frequencies up to 350 kHz. Their findings help designers select the optimal SiC devices for their high-frequency softswitching applications.

Why is the selection of an appropriate SiC device essential in ZVS applications?

Zero-voltage switching (ZVS) in a power converter is a key technique for reducing switching losses while mitigating electromagnetic interference, thereby enabling high switching frequencies of up to hundreds of kilohertz. ZVS is achieved by minimizing the voltage-current overlap during switching transitions through circuit parasitics or small passive-reactive components. Although ZVS significantly reduces switching losses, it does not eliminate them. In [1], it has been demonstrated that the remaining losses are influenced by the MOSFET’s intrinsic parameters (such as gate resistance, parasitic capacitances, etc.), as well as the gate driver’s drive strength and timing. The goal was to evaluate today’s leading 1200 V SiC power MOSFETs under ZVS in a half-bridge up to 350 kHz, providing clear device-selection criteria for designers of ultra-efficient, high-density soft-switching converters.

Image used courtesy of Adobe Stock

Testing Methodology Using a Transient Calorimetric Approach

Accurately estimating power losses from voltage and current measurements using double-pulse tests is highly challenging due to the rapid switching of WBG devices. Compared to electrical approaches, calorimetric measurement methods typically offer greater accuracy, making them more suitable for this context. To shorten the measurement time, a transient calorimetric method is employed. This method involves measuring the linear temperature rise ∆ϑ of a thermal mass — such as a copper block serving as a thermal capacitance Cth — heated by the transistor over a specified time ∆t (which is significantly shorter than the copper block’s thermal time constant). This allows for the estimation of total power losses in the semiconductor device using:

\[P_{loss,total}=\frac{\Delta\vartheta}{\Delta t}\,\,\,\,\,\,\,\,\,\,(1)\]

Test-Bench Setup

A 15-gram copper block is soldered to the back of each tested transistor to increase the thermal capacitance, as depicted in Figure  1(a). A half-bridge test circuit supplying an inductive load is used to assess the residual ZVS losses, as shown in Figure 1(b). The two switches, SHS and SLS, are operated using Triangular Current Mode (TCM) modulation to achieve ZVS turn-on for both the highside and low-side switches. The transistors’ dead-time is kept as short as possible to minimize the current flowing through the intrinsic body diodes. To further minimize conduction losses in the body diode during the dead-time, a SiC Schottky diode is connected in parallel with each transistor. The measurement setup utilizes three cylindrical air coils L, each with a distinct inductance value, to evaluate power losses at various switching frequencies ranging from 70 kHz to 350 kHz. The external gate turn-off resistor is set to zero, as is commonly practiced in soft-switched applications. The gate driver used in this study provides a maximum gate current of 10 A. The primary circuit and test parameters are listed in Table 1.

Figure 1. (a) Black-painted copper block soldered to a transistor. (b) Circuit diagram of the experimental setup featuring two transistors under evaluation. Image used courtesy of Bodo’s Power Systems [PDF]

Table 1. Experimental Circuit and Test Parameters.

Figure 2 illustrates an exemplary heating process in which the lowside switch is equipped with a copper block. Temperature measurements were taken on matte black painted surfaces to minimize surface reflections and thereby enhance the accuracy of thermal imaging. The temperature data were recorded using an infrared thermographic camera with an average sampling rate of 15 Hz. The slope of the recorded thermal profiles, along with Cth, determines the total power losses of the device.

Figure 2. Thermal imaging of a heating process. The measurement window is positioned at the center of the MOSFET die. Image used courtesy of Bodo’s Power Systems [PDF]

Table 2. Specifications of the SiC Transistors with TO-247-4 Package under Evaluation.

Experimental Results

Each device under test was operated for five seconds, starting at room temperature. Figure 3 presents the increase in copper block temperature obtained from thermal imaging.

The measurement series emphasizes the importance of selecting an appropriate transistor for soft-switched applications using ZVS: After five seconds, transistors T1 and T2 exhibit a temperature increase of only 4 K, which is roughly half the increase of 7.5 K observed in transistor T10.

The temperature profiles were recorded for each current level Isw at two different inductance values, corresponding to two distinct switching frequencies. Based on the temperature curves from thermal measurements, the conduction

losses can be subtracted during post-processing, allowing for the calculation of the residual switching energies under ZVS operation. The gate metallization losses were determined to be in the range of 0.5 to 2 µJ, which can be neglected in this study. Figure 4 presents the residual switching losses as a function of the switched current for all evaluated transistors.

Figure 3. Measured copper block temperature profiles over five seconds for various transistors switching at 40 A. Image used courtesy of Bodo’s Power Systems [PDF]

Figure 4. Calculated residual switching energies for the evaluated devices at different switched currents. Image used courtesy of Bodo’s Power Systems [PDF]

E_sw rises linearly to slightly more than proportional with increasing I_sw. Transistors T1 and T2 demonstrate the best performance in the investigation, while T7 and T10 show the worst results. In particular, the most suitable transistors for ZVS operation cause only about one-third of the switching energy compared to the worst. Minor anomalies in the E_sw-curves indicate slight measurement inaccuracies.

So, what’s the device selection criterion in ZVS applications?

Notably, the transistor’s unit cost did not correlate with its performance in the measurement series conducted. Instead, device-specific parameters determine the performance under ZVS conditions. A lower internal gate resistance R_g,int and a higher ratio of V_gs to V_th result in higher gate discharge currents.

For a given gate current, devices with lower input capacitance C_iss lead to a rapid gatesource voltage decay (small gate discharge constant τ_g(off)), and therefore remain in conduction for a shorter interval, resulting in a lower (V–I)-overlap. Consequently, transistors T1, T2, T3, and (at high load) T4 demonstrated superior performance.

Moreover, a larger output capacitance C_oss slows the vds rise during switching transitions, also reducing the overlap between voltage and current. For example, transistor T2 with its relatively high C_oss demonstrated particularly low losses compared to the others. In practical applications, further performance improvements can be achieved by adding an external NP0 MLCC capacitor in parallel to drain-source. This increases the effective capacitance and reduces voltage slew-rates, which particularly benefits otherwise lower-performing transistors. Beyond that, other transistor parameters such as transconductance and reverse transfer capacitance C_rss also impact the ZVS losses, although these effects are considered secondary.

The key findings highlight that minimizing R_g,int and C_iss, while maximizing C_oss, leads to the optimal ZVS switch. Sanan’s transistor portfolio is distinguished by its exceptionally low R_g,int down to 0.9 Ω, and a carefully optimized input to-output capacitance ratio. This synergy enables ultra-fast channel closure and a gentle voltage rise, reducing the (V–I) overlap during turn-off and minimizing residual switching losses under ZVS conditions.

The full article was published in the proceedings of this year’s PCIM Conference [1].

References

[1] T. Lehmeier, Y. Zhou, M. März, and A.P. Pai, “Influence of SiC MOSFET Device Parameters on Zero-Voltage Switching Losses,” in Proc. PCIM Europe, Nuremberg, Germany, 2025, pp. 1928–1934.

[2] Sanan Semiconductor, “1200 V 16 mΩ SiC Power MOSFET: SMS1200016M datasheet,” Rev. 1.0.0, 2024.

This article originally appeared in Bodo’s Power Systems [PDF] magazine and is co-authored by Thomas Lehmeier, Yan Zhou, Martin März, Institute of Power Electronics, Friedrich-Alexander-Universität Erlangen-Nürnberg, and Ajay Poonjal Pai, Head of WBG Innovation, Munich, Sanan Semiconductor