Technical Article

Performance Comparisons of SiC Transistors GaN Cascodes and Si Coolmos in SMPS

March 23, 2015 by Ing Artur Seibt

This article compares the performances of SiC Transistors, GaN Cascodes and Si-Coolmos in Switch Mode Power Supplies through extensive tests.

How do available SiC - transistors and GaN cascodes stack up against Si - Coolmos in real-world SMPS? Proven by extensive tests, neither SiC transistors nor GaN cascodes beat Si Coolmos. Alleged advantages of GaN are due to the cascode, not the material.


Introduction and Summary

The introduction of 600 V SiC diodes 15 years ago marked the first successful entry of a new material in power electronics. After more than a decade of perpetual announcements of SiC and GaN transistors and the imminent displacement of silicon, only SiC is firmly established.

GaN is heralded only by a wide variety of start-ups claiming fabulous advancements. Investors, notoriously impatient, expect high short-term gains, such statements hence should be pardoned to some extent, also because successful start-ups already failed after investors withdrew. The role and future of GaN is less clear. Unlike Si and SiC, GaN transistors are built on SiC or Si substrates so integration with control and other electronics is possible as is known from Si bipolars and MOSFET’s; this is an advantage, as this is not possible with Si Coolmos nor with SiC. GaN will probably find its niche in low and medium power applications, predominantly in lv buck ic’s and in bridge circuits. Displacement of Si will remain a fata morgana.

While single hv SiC JFET’s were on the market in 2011, no single hv GaN JFET’s are available. Enhancement GaN MOSFET’s up to 200 V are listed, 600 V types announced, but both are unavailable. Only 600 V Si MOSFET/GaN JFET cascodes in TO-247 and TO-220 are in stock. Eva boards, claiming “efficiencies of up to 99.3%” are offered. As a rule, App Notes and evaluation boards of semiconductor companies seldomly bear any resemblance to saleable products. Independent performance comparisons are not available. Scrutiny of the descriptions of those evaluation boards reveals, e.g., that the circuits are incomplete, and that the losses of all passive components, including the cables, as well as the auxiliary power are excluded, rendering them meaningless. Looking closer at the claims how much smaller a SMPS could be made with GaN cascodes, reveals that the SMPS used for the comparison is a ridiculously obsolete 50 KHz unit.

Knowing cascodes from wideband amplifier design and using them already since 1982 as superior switches in SMPS, the author suspected that the cascode and not the new material was the cause of the alleged better performance. This was supported by the fact that the GaN cascode manufacturers absolutely avoid the term “cascode”, trying to convey the impression of single transistors. Their comparisons of the cascodes with single Si Coolmos transistors are blatantly wrong. Users are easily led astray, because if one exchanges a single Si Coolmos for a GaN cascode, with 3 pins looking innocently like a single transistor, in many cases, shorter switching times and lower losses will result, misleading the user to believe in the superiority claims of GaN! Fallen victim!

Subsequent to SiC JFET tests in 2011, the author felt it was high time to again subject current SiC and GaN components to real-world tests in an offline SMPS. Result: The alleged advantages of GaN cascodes are due the cascode circuit, not to the material; with Si Coolmos in cascode better or identical results are obtained. SiC JFET’s as singles or in cascodes as well as MOSFET’s were at best as good as Si Coolmos. If engineers want to boost the efficiency of their designs, the author highly recommends to add a small lv Si MOSFET to the existing Si Coolmos and construct a cascode.

This statement applies to offline SMPS up to several hundred watts which is the majority. For higher power SMPS SiC MOSFET’s or Si MOSFET/SiC JFET cascodes will probably be the best solution. When the author confronted one GaN manufacturer with these results, he neither met with surprise nor contradiction.


Some GaN Claims

  • “...usher in a new era in power electronics...”
  • “... cost-effective revolutionary performance...”
  • “... transforming the future ... changing entire industries...”
  • “... GaN -based power technology stimulates revolution...”
  • “Redefining power conversion”
  • “... the advent of hv GaN-based power devices provides unprecedented opportunities to reduce both conduction and switching losses...”
  • “... wireless charging using GaN will eliminate wall sockets altogether
  • “... the company’s GaN transistors offer a 40-fold improvement in switching and conduction performance over traditional Si MOSFET’s and IGBTs...”
  • “... GaN FETs perfom 40 times better...”
  • “... promises to deliver performance FOM’s ten times better than state-of-the-art silicon...”
  • “... performance now 5 to 10 times better than the best commercial silicon...GaN will increase this gap to 1,000 times better...”
  • “..reducing the conduction losses by orders of magnitude...”
  • “... the specific on-resistance of GaN is orders of magnitude smaller than for Si or SiC...”
  • “... in the 600 to 1200 V range, GaN-based devices have the potential of improving Rdson by a factor of 1000 over Si MOSFET’s...”
  • “99.5% efficiency at 100 KHz in a booster with GaN”
  • “GaN reduces energy loss by 50 %.”
  • “... enables power conversion to > 50 MHz to 100 MHz without compromising power conversion efficiency...”

This list of hysterical hype could be extended. This certainly is a big mouthful; the language resembles advertisements for toothpaste rather than for electronic components. The announcements for SiC never used such language. Example: Regarding “... Rdson orders of magnitude lower...”: No SiC or GaN product with < 25 mOhms is available, but 19 mOhms Si Coolmos. Where are the 600 V 19 microOhms GaN’s?


What the propaganda doesn’t mention.

  1. The wrong comparisons of GaN cascodes to single Si Coolmos transistors constitute probably the worst misleading information! Cascodes must only be compared to cascodes. Even with bipolar transistors as upper transistors nanosecond hv cascode switches were realized decades ago.
  2. SiC and GaN components are not avalanche-proof! This is not mentioned in the documentation or in data sheets. JFET’s, by nature, cannot achieve avalanche-proofness. There are announcements for SiC MOSFET’s, promising a rating. These components can only be used in such circuits like PFC’s in which no over-voltages occur. In practice this means that either the breakdown rating must be far higher than that of an avalanche-rated Coolmos (1200 V equals 650 V) or protective components must be added, raising cost and deteriorating efficiency. In any SMPS there are also start-up, overload, short-circuit and input overvoltages to be reckoned with. Sincere statements are rarities: J. Roberts of GaN Systems, Canada, Bodo’s Power, July 2013: “It is necessary for you to recognize that our GaN transistors are similar to ceramic capacitors. That means that, at breakdown, they are destroyed. GaN devices have no avalanche specification. GaN devices have no repeatable, exercisable breakdown voltage capability.” He mentions that his audience was completely stunned which shows that this vital fact had not been communicated by the manufacturers!
  3. Most GaN’s are built on Si, some on SiC substrates, this means heat transfer is impeded compared to Si or SiC parts, also thermal conductivity is ¼ of SiC. GaN will thus never reach into the high power realm of SiC. The smaller chip size of SiC and GaN spells higher Rth and, due to the smaller volume, also a much lower overload withstanding capability.
  4. The low input capacitance of the GaN cascodes is a property of the cascode and not of GaN. The input is to the Si MOSFET gate, not to the GaN gate.
  5. The faster switching speed, compared to that of a single transistor, is a property of the cascode and determined by the Si MOSFET, not the GaN JFET!
  6. There are some failure mechanisms like “dynamic on-resistance” which manufacturers claim they have eliminated, only time will show whether this was true.
  7. Theoretical definitions like that of a “figure of merit” = Rdson x QG have no practical meaning in SMPS applications. The importance of Rdson is highly exaggerated, at SMPS frequencies, i.e. 100 to 250 KHz, the switching losses predominate. Example: In the tests decribed later, a 200 mOhm Si Coolmos cascode had the same losses as a 50 mOhm GaN cascode! Also, in a Si MOSFET/GaN JFET cascode, it is the gate charge of the lower transistor which is effective (no Miller effect); the gate of the upper(GaN) transistor is charged via the Rdson of the lower one plus the impedance of the resistance in the gate circuit.


Theory meets real world

Eating is the proof of the pudding is an old English proverb. What is the purpose, the measuring stick? It is efficiency, and, precisely speaking, overall lower losses, because the properties of a switching transistor or cascode also influence the losses in other components. Example: the introduction of SiC Schottky diodes in hard switching circuits like PFC’s not only decreased the diode losses but even more the switching transistor losses, because it turns on into an ac short as long as the diode does not switch off; with a SiC diode, the transistor can shrink by two sizes.

  1. The manufacturers argue as if their transistor or cascode was the only component in a SMPS. At least two components are connected to the drain of any switching transistor. Taking a PFC as example, a choke good for some hundred watts will have a substantial capacitance, even if a low capacitance winding is used (rare). The SiC diode is a Schottky and those suffer from high capacitance, e.g. a 600 V/6 A type will contribute from 300 to 30 pF from 0 to 400 V. The capacitances of the e.c. board conductors have to be added, they are capacitors with the e.c. board material as (lossy) dielectric. Consequently, the transistor’s output capacitance contributes only part of the whole capacitance, any reduction will be watered down. What counts is the performance in the circuit.
  2. The cascode is the fastest circuit, almost “too hot to handle”; installing one in place of a single transistor can lead to serious malfunctions because wiring and component placement on the e.c. board may not be commensurate with the increased speed! Erratic or chaotic performance may not even be noticed because regulation loops try to uphold the output voltage. It requires solid hf knowledge to fence the cascode in. It is irresponsible to offer cascodes without identifying those as such and warning customers!


Concise review of JFET’s and cascodes

Power JFETs, cascodes, the internal structures of power semiconductors, and how to handle them, the difficulties of precise efficiency measurements etc will be treated in detail, for the benefit of young engineers, in a later article.



FET’s were invented in the 1930’s, commercialized from the 1950’s as JFET’s and MOSFET’s, initially only for amplifier and analog switching purposes. Whereas MOS ic’s appeared shortly after bipolar ic’s, there are no JFET ic’s, however, they were integrated early in bipolar ic’s, e.g. in operational amplifiers and analog switches. Si power JFET’s were manufactured by 4 Japanese firms. JFETs consist of a channel and a pn diode between gate and channel which is normally off; at zero volts the channel is fully conducting, if a voltage higher than the pinch-off voltage is applied, the channel will be cut off. If a positive voltage > 0.6 V is applied, the diode will conduct and connect the gate to the channel. JFET’s are unipolar devices and hence, depending on transconductance and capacitances, useful into the GHz region. By nature, a JFET cannot take overstress, overvoltage will cause a drainto gate diode breakdown.


Cascode circuit

In 1939 F.V. Hunt und R.W. Hickman described the function of a cascode and it was commonly used in all tv sets’ and fm radios’ input stages from the 1950’s. The cascode is also an ideal extremely fast and efficient power switch which merits due recognition by SMPS designers.

The term “cascode” was coined from “pentode” and “cascade”, any two (or more) active devices can be hooked up as a cascode. If two devices of dissimilar polarity are used, a socalled “folded” cascode can be constructed which allows, e.g., that input and output are on the same level. It combines a grounded emitter or source transistor with a grounded base or gate transistor in ac, not necessarily also dc, series connection. This way an “ideal” compound transistor is created.


Basic cascode connection combines a grounded source transistor with a grounded gate one, creating an ideal compound transistor

Figure 1: Basic cascode connection combines a grounded source transistor with a grounded gate one, creating an ideal compound transistor


  1. The lower transistor operates into an ac short which is the source input impedance (1/S) of the upper one, hence there is no ac voltage at its drain and consequently no Miller effect. The input capacitance is the lowest possible for a grounded source stage and consists only of the sum of the gate-to-source plus gate-to-drain capacitances, it is easier and faster driven. Due to the high transconductance of Si power MOSFET’s the Miller effect is severe in the basic grounded source circuit which slowes the switching down and requires high current, low-impedance drivers. If logic level MOSFET’s are used, the transconductance will be still higher. With the drain effectively grounded, the transistor achieves its highest speed. Please note: the properties of any cascode are determined by the lower active element.
  2. The upper grounded gate transistor does nothing else but to pass the ac current of the lower one along to the output, its drain, and to establish a shield between the output and the input. As far as speed is concerned, It is fairly immaterial which kind of transistor sits there. This is best understood if one assumes there is a bipolar transistor: in grounded base its alpha = 1 and its alpha or fT - cut-off frequency are effective. Si bipolar power transistors with fT ‘s of several GHz are common. FET’s as unipolar devices know no cut-off frequency, their limit is given by transconductance and capacitances, eventually by transit time limitations. This way amplifiers with GHz bandwidths are realized. A switching circuit is nothing else but an overdriven amplifier, and, remembering the basic formula: rise time = 0.35/bandwidth, a bandwidth of e.g. 1 GHz equals a rise time of 0.35 ns. Consequently, also the properties of a Si MOSFET/GaN JFET cascode are determined by the Si MOSFET and have almost nothing to do with the GaN JFET! The speed one sees is the speed of the Si MOSFET and not that of the GaN JFET! The speed of Si MOSFET’s is often misrepresented and far underestimated.
  3. The only contribution of the GaN JFET is its perhaps lower output capacitance; if that is lower than that of any other type of transistor in its place, the total node capacitance will be a little lower and thus the speed a bit higher.
  4. The impedance in the source of the upper transistor is equal to the drain output impedance of the lower one which causes strong feedback; the output impedance of the upper one approaches hence infinity. In amplifiers extremely high stage gain can be achieved. It is mandatory to minimize the capacitance between output and input, otherwise serious Miller effect will spoil the performance. This is easy to accomplish in cascodes made of individual transistors by setting them apart; the connection carries only a current signal, so its capacitance is of lesser importance. If both are in one package the inductance is minimized, but the distance between input and output closest.
  5. The fast switching is the cause of the lower losses. In general, the fall time will be the shortest in most circuits, it is typically 10 to 5 ns. The rise time is mostly determined by the circuit. Example: a simple PFC: Assuming the SiC diode and the cascode switch in zero time, the node capacitance can only be charged up to the input voltage through the choke which is a constant-current generator


Si MOSFET/Si Coolmos cascodes are superior, they retain the avalanche-proofness and profit from decades of design and manufacturing knowhow as well as low price, abundant supply, second-sources, established reliability etc. More than a perhaps slightly lower output capacitance these GaN cascodes can not bring to bear, this is at best neglegible, compared to an impressive list of disadvantages: The life expectancy of start-ups is at best questionable, supply is by no means guaranteed, there are no second-sources and hence no competition which spells high prices. The quality and reliability of GaN are at best questionable and will take years to establish. In most companies design in of such unproven single-source components with shaky supply is not allowed; the risks of incorporating such parts in series products are too high. The author recommends to Si Coolmos resp. superjunction manufacturers to bring 4-pin cascodes to market which would be superior to and much less expensive than GaN cascodes. The 4th pin is necessary because power MOSFET’s are enhancement types, the gate of the upper one has to be tied to + 12 to 15 V.

If the alleged advantages of GaN were real, the logical step would be to use an enhancement GaN MOSFET as the lower transistor and a Si Coolmos as the upper one in order to combine the best of both worlds. Considering that lv enhancement GaN’s are said to be available for some years, it is hard to understand why such cascodes aren’t offered, or GaN eMOSFET/GaN JFET cascodes.


Bipolar bridge circuits

In many bridge circuits current must also flow in reverse direction which is a problem for Si MOSFET’s because they suffer from the parasitic antiparallel diode which is the CB diode of the parasitic npn. JFET’s conduct equally well in both directions and are free from parasitic elements. JFET’s were used from the beginning also as switches, this property is independent of the material. SiC power JFET’s are available since years. Any enhancement MOSFET/JFET cascode is eligible as a bipolar switch: Reverse current will flow through the antiparallel diode of the MOSFET, this is a low voltage type, so the diode is very fast. What then is the difference between Si and SiC JFET’s and GaN JFET’s, if any? Si and SiC JFET’s use a pn diode between gate and channel which is always reverse-biased unless the gate is overdriven in positive direction; in such case, there will be a connection between gate and channel.

With GaN JFET’s, the gate is dielectrically isolated from the channel, similar to MOSFET’s. How much bias is safely applicable in both directions is not disclosed and can not be measured in the available cascodes. Hence there is no connection between gate and channel even if overdriven in positive direction. This seems to be the only difference. Why that should be an advantage in practice over Si and SiC is hard to see, because it is only a matter of the gate drive circuit to prevent positive overdrive, also in many cases this will not harm. Because SiC also provides low Rdson and fast switching and is far better suited to such service it is to be expected that Si MOSFET/SiC JFET cascodes will become available and compete with those GaN cascodes.


Samples and Test Vehicle

Only products available from distributors were eligible. In 2011 SiC JFET 1200 V samples in TO-247 of various sizes were tested, in 2014 600 V GaN cascode samples in TO-247 and TO-220 with 50, 160 and 320 mOhms and SiC MOSFET 1200 V TO-247 samples with 75, 85, 50 mOhms and 600 V/0.13 ohms in TO-220.

A 200 W offline wide-range SMPS with 6 output voltages, PFC and FB converters was chosen. Both converters are driven by a low-cost bipolar combo ic at 125 KHz for emi reasons. This SMPS originally uses an Infineon Coolmos 600 V/0.38 ohm 11N60C3 in the PFC and a 650 V/0.38 ohm 11N65C3 in the FB. The PFC uses a SiC 6 A diode, the 6 outputs 6 and 2 A SiC diodes. As described in the author’s paper in Bodo’s Power, Nov. 09, SiC Schottky diodes excel also as secondary diodes down to appr. 25 V.

The GaN cascodes and single SiCs were first tested against the original C3’s, then against the most recent CP and C7 with 600/ 650 V and 200,125 and 100 mOhms. Because these already turned out to be superior, the lower Rdson Coolmos types were not even tested.

All samples were tested in the PFC at 365 V, only the 1200 V SiC and the 650V Si Coolmos could be tested in the FB with a peak voltage of 740 Vp. Each transistor resp. cascode was tested with 3 different drive circuits: 1. direct drive out of the rather slow bipolar outputs of the combo ic (1 to 11 V at 13 V Ucc) - 2. via an intermediate Harris 7667 CMOS gate driver ic with 7 ohms - 3. operated in cascode. The SiC MOSFET’s asked for 18 V signals, for these an IR 2110 CMOS gate driver was used. Cascode connection is - as regards losses - practically equivalent to a very fast low-impedance direct drive. With each test, time for thermal equilibrium was allowed. Please note: Input power figures may only be compared within the same test series. No attempt was made to test for an optimum lower Si MOSFET in the cascodes. These tests took an enormous amount of time anyway.


Comparisons with Si Coolmos C3

2011 tests of SiC - JFETs 1200 V, 85 and 45 mOhms

Considering the claims of much lower capacitances first a simple direct drive circuit with an external - 12 V supply was used. In the first test series, only the PFC was operated into a dummy load, With fairly slow rise and fall times at the gate the losses were identical to the single Coolmos’ at ¼ load, slightly higher at ½ load and 1.2 load.

A faster direct drive would have been more complicated than a cascode, so this was installed in the continuous-conduction mode FB because there were the higher stresses and losses. For the lower transistor a 80 V/16 mohm Si - MOSFET in TO-263 was chosen. The drive signal was identical to that of the original Coolmos. The higher input power at 115 V line was chosen for the comparisons:

  • Coolmos C3 0,38 ohms, directly driven: 222.7 W
  • SiC 85 mohm JFET in cascode 220,4 W
  • SiC 45 mohm JFET in cascode 222 W
  • BUT: Coolmos C3, also in cascode 220,9 W
  • Rise time 30 ns to 700 Vp, fall time 12 ns.


If both SiC JFET and Si Coolmos are operated in cascode, the losses are almost identical. This is no surprise, because the same lower Si MOSFET was used. Please note that the Coolmos is 380 mOhms and obsolete by 3 generations while the SiC’s are 85 resp. 45 mOhms! The 45 mOhm chip is too large for 200 W. These SiC JFET’s have lower capacitances than the SiC MOSFET’s tested in 2014.


Tests of GaN - JFET - cascodes 600 V/0.32, 0.16 ohms in the PFC

All following tests were performed from Sept. to Dec. 2014. Again the PFC with 365.2 V output voltage was operated into a precision dummy load of 200 W. The power at 115 V line was used for comparison. (The figures include an auxiliary SMPS.) Due to the 600 V spec and the missing avalanche-proofness a test in the FB was impossible. The direct drive signal comes again from a bipolar combo and is fairly slow from 1 to 11 V.

  1. Coolmos 11N60C3, 0,38 ohms, driven directly: 217.2 W, 12 ns, 35 ns.
  2. Same, driven via Harris 7667 CMOS high current driver: 213.7 W, 12 ns, 8 ns.
  3. Same, cascode: 213.6 W, 10 ns, 8 ns.
  4. Larger chip 20N60C3, directly driven: 216.8 W, 18 ns, 42 ns.
  5. Same, in cascode: 214.3 W, 18 ns, 8 ns.
  6. GaN - cascode 600 V/0.16 ohms, directly driven: 213.9 W, 16 ns, 16 ns.
  7. Same, driven via 7667: 213 W, 16 ns, 8 ns.
  8. GaN - cascode 600 V/0.32 ohms, directly driven: 213.8 W
  9. Same, driven via 7667: 212.6 W, 10 ns, 7.5 ns.

Result: Compared to the 0.38 ohms Coolmos C3, also in cascode, with 213.6 W the 0.32 ohms GaN cascode, with the identical direct drive, shows 213.8 W, if driven extremely fast by an additional 7667 CMOS high current driver 212.6 W can be achieved, i.e. 1 W less than with the Coolmos. However, no test was made with the Coolmos C3 in cascode and also driven fast, The 0.32 and 0.16 ohm GaN’s had almost identical losses, proving again the minor importance of Rdson in SMPS. The lower Rdson was offset by the higher capacitances of the larger chip.


Tests SiC - MOSFETs 1200 V/85 mohm and 600 V/0.13 ohm in the PFC

Available samples required a 18 to 22 V gate drive, not available from standard SMPS ic’s. An IR 2110 20 V CMOS or a Harris 7667 7 ohm CMOS high current driver was inserted between the slow bipolar output and the test object.

  1. SiC - MOSFET 1200 V/85 mohms, with a gate resistor of 2.2 ohm in parallel with a 4150 diode: 214.8 W, 25 ns, 25 ns.
  2. SiC - MOSFET 600 V/0.13 ohms, directly driven (only 1 to 12 V): 220 W.
  3. Same, driven via IR 2110, 15 V, gate resistor 50 ohms//4150: 216.4 W, 30 ns, 70 ns.
  4. Same, 15 V, 7667 driver, 7 ohms: 214.2 W, 35 ns, 30 ns
  5. Same, 18 V, 2110 driver: 213.4 W
  6. Same, 18 V, appr. zero gate resistor: 212.8 W, 10 ns, 18 ns.
  7. Same, cascode, 15 V, via a 25 ohm resistor: 214.6 W, 18 V: 214.4 W. This measurement was performed very quickly. Without a S to G diode the source rose to 80 Vp.
  8. Same, but a diode S to G added, 10 ohm gate resistor: spike reduced to 35 V, after a few seconds smoke, destruction. The maximum permissible gate voltage is - 6 to + 22 V. MOSFETs normally take equal voltages on the gate like +- 20 V. If the source goes up to 80 or 35 V, this means - 62 resp. - 17 V negative gate voltage. Obviously, these parts can not be used in a cascode connection. As the drain spike is clamped at 740 Vp, gate oxyde breakdown is the probable cause.


Test SiC - MOSFET 1200 V/0.3 ohm in the FB

The transistor was tested in the FB in place of the 11N65C3, however via the high current IR 2110 driver at 18 V.

PIn (115 V) = 216.8 W vs. 218 W with the original Coolmos. Rise time 35 ns to 720 Vp, fall time 35 ns. Gain, at first sight: 1.2 W. But the Coolmos, in the original circuit, is driven by the fairly slow signal out of the bipolar combo ic; if operated in cascode its losses drop by 1.8 W.

Result: For a fair comparison the Coolmos must also be driven fast, then its losses are indeed 0.6 W lower than those of the SiC in cascode.

Circuit changed to cascode with a 80 V/16 mohm Si - MOSFET, the gate at 18 V: at turn-on loud noises, smoke and smell: the SiC, the Si - MOSFET, gate resistor and the T 2.5 A input fuse destroyed, the contact of a relay, bridging a 10 ohm current limiting resistor in the line input welded. Again proof that these parts must not be operated in cascode.


Comparisons with state-of-the-art Si Coolmos CP and C7

The CP and C7 series are designed for fastest switching and improved efficiency, the high Rth of 2 degr./W points to chips of half the size of the former series


Comparisons in the PFC

As before PIN (115 V) figures, 365 V, PFC into dummy load 200 W, auxiliary SMPS included.

60R199CP, 200 mOhms, direct, 22 ohms//4150: 213,8 W 12 ns, 20 ns

Same, via 7667 driver, 22 ohms//4150: 212,1 W 12 ns, 9 ns

Same, cascode, 10 ohms in gate, 47 ohms//4150: 212,8 W 10 ns, 12 ns

Same, cascode, driven by 7667 212,5 W 13 ns, 11 ns


GaN cascode 50 mOhms, direct, 22 ohms//4150 212,0 W 20 ns, 14 ns

Same, 47 ohms//4150 212,2 W

Same, appr, zero ohms 211,7 W 20 ns, 12 ns.

Same via 7667 driver, 22 ohms//4150 211,5 W 20 ns, 5 ns Because of too much 140 MHz ringing 35 ohms 211,7 W 20 ns, 6,5 ns


SiC MOSFET 1200 V80 mOhms, direct 47 ohms//4150 (direct = 1 to 11 V only) 218,2 W 50 ns, 130ns

Same 10 ohms 215,2 W fall time 50 ns

Same, appr. zero ohms 213,7 W, 30 ns.


60R099CP, 100 mOhms, 7667, 47 ohms//4150 213,0 W

Same 22 ohms 212,5 W 18 ns, 12 ns

Same 10 ohms 212,2 W

Same, direct, 47 ohms//4150 213,6 W 22 ns 22 ns

Same, cascode, 47 ohms 213,2 W 17 ns 10 ns


65R190C7, 190 mOhms, direct 47 ohms//4150 213,4 W

Same 10 ohms 213,2 W 15 ns 23 ns

Same via 7667, 47 ohms//4150 212,0 W

Same 9 ohms 211,7 W 20 ns 7 ns

Same, appr. zero ohms 211,7 W 20 ns 6 ns


65R125C7, 125 mOhms, via 7667, 47 ohms//4150 212,3 W

Same, 10 ohms 211,7 W 20 ns 7 ns

Same, direct, 47 ohms//4150 213,2 W 20 ns 24 ns


Results: These comparisons show how much the results are dependent on the drive, the damping resistor in the gate and whether single or in cascode. Also, in cascode, the protection diode resp. zener influences the losses. The GaN cascode with the lowest Rdson available (50 mOhms) has losses identical to those of the Si Coolmos 190 mOhms and 125 mOhms, if also operated in cascode!


9.2 Comparisons in the FB

The lower PIN (230 V) figures were taken for comparison. In the cascodes, a 80 V/16 mOhm Si MOSFET was used. The tests showed that the new Coolmos types have been drastically improved with respect to their capacitances, the Rdson’s are half of C3, because, even with the slow drive, their losses are lower than those of the C3. They show, on the other hand, the low influence of the upper transistor in a cascode.

11N65C3 for reference, direct, 15 ohms//4150: 212,7 W

Same, cascode, 15 ohms //4150: 210,7 W, 28 ns, 45 ns.

65R125C7, 125 mOhms, direct, via 15 ohms//4150: 210,5 W, 37 ns, 75 ns. 65R190C7, 190 mOhms, direct, 15 ohms//4150: 210,5 W, 30 ns, 80 ns.

Same, cascode, 210,0 W, 25 ns, 18 ns.

Same, via 7667 driver: 209,6 W

SiC MOSFET 1200 V/80 mOhms, direct, only 1 to 11 V, 15 ohms//4150. The higher output capacitance was visible: 214,4 W, 90 ns, 80 ns.


About the Author

Dr.-Ing. Artur Seibt is a professional electronics design lab consultant with specialization in SMPS with 40 yrs. experience incl. SiC, GaN, D amplifiers. Inventor of current-mode control (US Patent) and He is also an expert in EMI design.