Maximizing Performance with SiC DiscretesFebruary 13, 2019 by Anup Bhalla, UnitedSiC
UnitedSiC has recently expanded its SiC FET product offerings to encompass devices with tailored switching speeds
UnitedSiC has recently expanded its SiC FET product offerings to encompass devices with tailored switching speeds and offered both in traditional 3-leaded packages as well as a range of packages with source Kelvin. These devices target a wide range of applications, including on-board chargers, battery chargers, industrial power supplies, PV inverters, server power supplies, telecom rectifiers, and high-power lighting.
The typical circuit topologies encountered in these applications include active frontend 3-phase rectifiers, totem-pole PFC stages, interleaved PFC circuits, phase shift full bridge, LLC and dual active bridge circuits. Given their excellent low on-resistance, fast switching speeds and low VF, low Qrr intrinsic diode performance, these devices can be used in all these topologies and applications. Since system layout, thermal, power density and EMI constraints are quite varied, it is useful to know some simple tips to extract the highest performance from these devices.
UnitedSiC's Expanded Portfolio
Figure 1 shows the organization of the UnitedSiC portfolio, which spans a full range of JBS diodes 650-1200V, SiC JFET, and SiC FETs. The SiC FET portfolio consists of highly optimized cascoded devices, that co-package a customized Silicon MOSFET with a low specific on-resistance SiC JFET in thermally enhanced “standard” packages. The devices are now offered in two speed classes by adjusting the SiC JFET switching speed via gate resistance adjustment.
The UJ3C series is slower switching and has higher Qrr, but is easier to use in standard 3-leaded packages. The UF3C devices are about 2X faster and offered in both 3-leaded and Kelvin source type packages. They require more careful attention to circuit layout, and benefit from the use of RC snubbers, especially for 3-leaded packages with high common-source inductance.
Figure 1. Portfolio of SiC products from UnitedSiC. The faster UF3C series is available in various 3-leaded and Kelvin sourced options, while the slower UJ3C series is designed for ease of use in standard 3-leaded packages.
The TO247-4L package adds a source Kelvin connection to the standard TO247-3L. This allows the user to overcome the limitations imposed by common source inductance and enables faster switching speeds and higher dI/dts, with clean gate waveforms and no false triggering. However, the loop inductance of half-bridge configurations implemented in these packages stays quite high, in the 20-30nH range, and leads to high voltage overshoots. To mitigate the overshoot and damp ringing after FET turn-off, small RC snubbers may be employed. The D2PAK-7L package is for surface mount applications and provides much-reduced package and half-bridge loop inductances. This is further improved in the DFN8X8 package, where loop inductances can be reduced 6-8nH.
Unique Aspects of SiCFETs
A key factor that enables the formation of high-performance cascode structures is the use of JFET device structures with near zero CDS values. This prevents the formation of a capacitive voltage divider between the low voltage MOSFET and the SiCFET.
The low voltage MOSFET is optimized for a +/-25V VGS(MAX), and a 5V Vth. This allows the gates to be driven with a 0 to 12V gate drive in most cases. The wide gate operating range, and absence of Vth hysteresis and -VGS instabilities relative to conventional SiC MOSFETs means that it is possible to use the cascoded SiCFET at the gate voltage drive level of Superjunction MOSFETs, IGBTs or any type of SiC MOSFET, with larger safety margins on the gate voltage. Added ESD protection features on the gate improve production reliability, but also serve to clip voltage spikes above +/-25V without the need for external zeners.
Cascode devices are built so the MOSFET external Rg is used to slow the VDS swing of the low voltage MOSFET. This in turn acts like the VGS drive for the normally-on JFET, and offers a level of dV/dt and dI/ dt control. The UJ3C and UF3C series extend the range of dV/dt control by using JFETs with differing internal RG. The UJ3C series covers moderate dV/dts of 20-40V/ns, while the UF3C series is useful in the 40-100V/ns range. As packaging technology and integration improve, these speeds can be further enhanced up to the fundamental dV/dt peak speed of dV/dtMAX=IL/COSS, the rate at which the load current can charge the device output capacitance.
Using Fast Devices in 3-Leaded Packages
UnitedSiC UJ3C and UF3C devices are compared in Table 1. The speed improvement of the SiC JFET allows faster turn-on and turnoff, and in the cascode configuration, it also improves the Qrr. It is clear that switching speeds are improved and switching losses can be much reduced using UF3C devices.
Table 1. A comparison of the UJ3C and UF3C devices for conduction loss and Qrr.
The normally-on SiC JFET technology employed in these devices features very low specific on-resistance (RdsA) for both 650V and 1200V classes. This leads to small chip sizes, which in turn leads to reduced output capacitance COSS values. Therefore, if an RC snubber is needed, a relatively small value of CSNUB will do the job, typically arranged with surface mount components in parallel with the source and drain of the FET as shown in Figure 2.
Figure 2. A Double Pulse test circuit with RC snubbers used for EON/EOFF measurements.
Figure 3 shows a comparison of the device switching waveforms with and without the use of an RC snubber. In practical applications, the need to simplify heatsinking may result in layouts that are not optimal for total loop inductance. Gate drive loops may also be hard to keep tight, depending on overall converter shape and size considerations. To avoid switching issues with fast switching SiC transistors, small RC snubbers can be employed to great effect.
Figure 3. UF3C120040K3S turn-off without snubber (top), with snubber (bottom) at VDS 800V, ID 50A, VGS -5V, Rgoff 33Ω. CH2: ID 20A/div); CH3: VGS (10V/div); CH4: VDS (200V/div).
As shown in Figure 3, the use of a modest 220pF, 10ohm snubber can dramatically improve the voltage/current ringing. This, in turn, improves the VGS waveforms, since most of the noise on the gate waveforms stems from the current ringing acting on the internal common source inductance (which is high in the TO220-3L and TO247-3L packages). Snubber loss is measured by integrating the voltage drop across the resistor during turn-on and turn-off and amounts to just 2.5% of EON+EOFF at 10A, 800V and 1.5% at 50A, 800V. A 2W resistor is sufficient up to 50kHz hard switched operation. At higher frequencies, two resistors may be used in series to dissipate additional power.
At high currents, turn-on dI/dt can be increased by increasing gate voltage drive level from 12V to 15-20V. This reduces EON losses, and in the presence of the same snubber, switching waveforms are well controlled. RG values are suggested for a wide range of gate drive operating voltages in the UnitedSiC user guide, as are values for snubber R’s and C’s. These techniques can help users extract the maximum benefit from the UnitedSiC FET line-up, and design circuits to allow the use of existing SiC MOSFETs and UnitedSiC FETs with no change to gate drive levels.
Pushing to Higher Speeds
While the use of Kelvin source packages is still not dominant in the part of the industry deploying SiC MOSFETs, the benefits of these packages in improved performance means that over the next few years, they are poised to increasingly dominate, especially as multiple suppliers come online. Figure 4 explains the basic problem caused by the inclusion of the common-source inductance within the gate drive loop, and how the use of the source Kelvin bypasses any voltage drops developed across this inductance during fast dI/dt transitions. Those voltage drops always work to slow down turn-on and hold up the gate to keep the device on during turn-off.
Figure 4. The circuit on the left shows how the common source inductance can reduce the voltage available at the FET gate-source due to di/dt induced voltage drop. This voltage drop is high because both the load and gate currents pass through this inductance. On the right, with a Kelvin pin available to return the gate current, the large voltage drop induced by the main load current in the common source inductance no longer debiases the gate.
Figure 5 below shows improvement in the gate waveforms using the Kelvin source package, while simultaneously switching on and off faster, with lower losses for the 35mΩ, 1200V FET. The losses are inclusive of the snubber loss. A set of switching waveforms at 50A, 800V on the UnitedSiC double pulse demonstration board is shown in Figure 6. It is interesting to note that an even smaller snubber capacitance is used here, just 115pF for this high current 1200V, 35mΩ FET. Again, the UnitedSiC user guide provides values of RGs for various gate drive voltage levels and suggested RC snubbers for the Kelvin type package options as well.
Figure 5. Comparison of VDS, ID waveforms (top row) and VGS waveforms (bottom row) using the same chipset in the 3-leaded (Dashed lines) and 4-leaded packages (Solid lines). Data is taken in a inductive load double pulse circuit with RSNUB=10ohm, CSNUB=220pF, RGON=3Ω, RGOFF=10Ω, 40A, 800V, Gate drive -5V to 15V.
Figure 6. UF3C120040K4S turn-off (above) and turn-on (below) waveforms with snubber. CH1: CH2: ID (20A/div); CH3: VGS (10V/ div); CH4: VDS (200V/div). (VDS 800V, ID 50A, 125°C, VGS 20V/-5V, RGON 50Ω, RGOFF 33Ω, snubber CS 115pF, snubber RS 10Ω).
A wide range of available isolated gate drivers are available for use with such source Kelvin packages, since the return for the gate is no longer at the power source potential. The gate drive power rails must therefore also be isolated, or the gate driver must be able to withstand some voltage bounce between source and Kelvin-source connections. Considering the low side FET for example, it is easy to see from Figure 4 that the gate drive power rails have a transient with respect to the power ground, equal to the drop in the common source inductance. This can be as high as 5-10V, depending on the operating dI/dt.
For circuits driven directly by control ICs with built-in drivers, if a current sense resistor must be used in series with the Kelvin-source device, the drive circuit must be adapted to ensure that only the differential voltage across that current sense resistor is seen by the control IC.
Comparing Kelvin Source Packages
In Table 2 below, we compare the switching behavior of a 30m, 650V FET being hard switched in a half-bridge at the same 20A, 400V condition in three packages, the DFN8x8, D2PAK-7L, and TO247-4L. The package size increases from DFN8x8, to D2PAK-7L and finally the TO247-4L.
Table 2. Comparison of switching behavior of the 30m, 650V FET in three Kelvin source package options, at 20A, 400V.
Power loop inductance is therefore usually highest with TO247-4L, lower with D2PAK-7L and lowest with DFN8X8. The thermal dissipation capability is highest with TO247-4L and lowest with the DFN8X8. The lower half of the table shows the switching data compared with a 10ohm, 220pF snubber across each FET. This helps manage the voltage overshoots that are highest for the TO247-4L case.
To provide designers with maximum flexibility, depending on the target operating frequency and circuit topology, all these options will be available in the UnitedSiC FET portfolio to meet user needs.
UnitedSiC's Gen 3 Product Portfolio
UnitedSiC’s Gen 3 product portfolio of FETs and Diodes are now available in a wide array of packages. Two speed classes of FETs are offered, the slower UJ3C series and the faster UF3C series. The faster series is also offered in packages with source Kelvin connections. The small output capacitance of the FETs allows the use of small low loss snubbers to manage very fast switching waveforms, with minor loss impact. A wealth of information on how to use the devices is available. Happy switching!
About the Author
Anup Bhalla works as the Vice President of Engineering at United Silicon Carbide, Inc. where he is responsible for commercializing SiC-based Diodes, trench vertical JFETs, BJTs, trench vertical MOSFETs, GTOs and ICs. He earned his Bachelor's Degree in Electrical Engineering at the Indian Institute of Technology. He also holds a Master's Degree and Doctorate Degree in Electrical Engineering both earned at the Rensselaer Polytechnic University.
This article originally appeared in the Bodo’s Power Systems magazine.