Fighting Bipolar Degradation With High-Performance SiC Substrates

This article is published by EEPower as part of an exclusive digital content partnership with Bodo’s Power Systems.

The need for more and more power electronics applications, with higher power densities and requiring high availability over longer operating times, puts tremendous pressure on the device characteristics, which not only need to present an enhanced performance but also higher reliability.

In power applications, it is usual that switches need to conduct current passively in reverse mode operation. Though in systems based on IGBTs, this functionality is ensured by, most commonly today, SiC diodes, when SiC MOSFETs are used, reverse conduction is carried out by the body diode of the same transistor. By construction of SiC MOSFETs, their body diode is of PiN type, as shown in Figure 1.

It has been widely observed that bipolar currents through a 4H-SiC crystal contribute to the generation and expansion of recombination-induced stacking faults (SF), being the root cause mechanism for R_DSon increase, known as bipolar degradation. This degradation occurs under high bipolar current density stress. Holes injection close to the BPD (basal plane dislocation) to TED (threading edge dislocation) conversion point, or along the BPD itself in the epitaxial stack and underneath the SiC substrate, trigger a glide of one component of the BPD. This gliding generates Shockley stacking faults (SSF) that expand along the basal plane. The area of the device covered by those SSFs presents a significant increase in the device’s R_DSon. This specific robustness issue is mainly predominant for current densities above 500 A/cm². This failure mechanism, contributing to an increase in the conduction power losses, affects SiC MOSFETs when the body diode is forward-biased.

Figure 1. Basic structure of a planar SiC MOSFET showing the PiN body diode (left) as well as the equivalent schematic diagram (right). Image used courtesy of Bodo’s Power Systems [PDF]

Protecting Against Bipolar Degradation

It has been recently identified that proton implantation has the capability to block Shockley stacking faults (SSF) expansion in 4H-SiC substrates, making devices manufactured on irradiated substrates virtually immune to bipolar degradation.

Those studies from Prof. Harada and Prof. Kato from, respectively, Nagoya University and Nagoya Technology Institute clearly evidenced that high dose (>10¹² H+/cm²) proton implantation on the bare 4H-SiC substrate can strongly reduce this bipolar degradation by stopping the propagation of SSFs. Though the root cause is not yet fully identified, current hypotheses consider two possible phenomena. One is that the implanted protons create the conditions to shorten the minority carrier's lifetime. A second hypothesis suggests that the implanted protons pin the basal plane dislocations.

SmartSiC engineered substrates are obtained through the Smart Cut process. This process is schematized in Figure 2. During this process, after the surface preparation stage (2), the single-crystal 4H-SiC donor wafer is implanted with protons (stage 3), with a dose in the order of 10¹⁶ (H+/cm²), which is in the higher range of those employed by Prof. Harada and Prof. Kato.

Figure 2. Smart Cut process adapted to silicon carbide. Image used courtesy of Bodo’s Power Systems [PDF]

Material Robustness

To investigate the potential robustness of SmartSiC engineered substrates against bipolar degradation, in collaboration with the Naval Research Laboratory (NRL), we grew 10 µm-thick epitaxial layer on top of a 2 µm (10¹⁸ at./cm³) conversion buffer on SmartSiC engineered substrates, as well as on standard singlecrystal 4H-SiC wafers. This stack of epitaxial layers is identical to the one utilized on 1200 V SiC MOSFETs.

As a result of the experiments, a drastic reduction of SSF expansion in SiC-engineered substrates has been observed for UV fluences up to 10 kW/cm² (Figure 3), two orders of magnitude higher than the ones applied in other experiments.

Figure 3. Comparative SSF expansion after 10kW/cm² UV exposure (reproduced with the permission of N. Mahadik, Naval Research Laboratory). Image used courtesy of Bodo’s Power Systems [PDF]

After the first indications at the material level that engineered substrates offer a substantial advantage over single-crystal wafers, full corroboration was obtained through experiments carried out on 10 A, 1200 V PiN SiC diodes (DUT). DUTs, as shown in Figure 4, were implemented using Al-implanted P+ guard rings and a junction termination extension (JTE) to achieve the target breakdown voltage. Implanted Al has been annealed at 1700 ºC. The substrates were not thinned (final thickness at 350 µm) and backside ohmic contact formation was performed using laser annealing. A total of ten devices made on SmartSiC engineered substrates and eight devices made on standard single-crystal SiC wafers were tested.

Figure 4. Picture of the 10 A, 1200 V PiN diode prepared on a SiC-engineered substrate. Anode active area: 2 mm². Image used courtesy of Bodo’s Power Systems [PDF]

DUTs were attached to a DBC substrate through soft solder and water-cooled from the backside of the substrate at a coolant temperature of 25°C. DUTs were then stressed at a high forward current using a pulsed mode set-up developed by the Fraunhofer IISB. Current pulses of 600 µsec with a peak value of 45 A (current density of 2250 A/cm²) were applied, separated by a cooling period of 150 msec. Just after every 600 µsec stress pulse, a low current is injected into the PiN diode to monitor the DUT junction temperature through the forward voltage drop. During the stress phase, 600k cycles (stress pulse + cooling period) were applied, corresponding to a cumulated stress time of 360 sec. The stress setup is shown in Figure 5.

Figure 5. Stress setup showing the DUT mounted on the DBC. Image used courtesy of Bodo’s Power Systems [PDF]

Pre- and post-stress DUT characterization was performed through a four-point probe setup. To evidence the effect of bipolar degradation on the DUTs, the evolution of the I(V) curve before and after stress for all devices made on both types of substrates was obtained. The amount of bipolar degradation is quantitatively determined as the shift of the forward voltage (∆V_f = V_{f_post-stress} - V_{f_pre-stress}) at a forward current of 15 A. Typical I (V) curves for pre and post-stress conditions for a reference DUT made on single-crystal 4H-SiC are shown in Figure 6.

Figure 6. Typical pre- and post-stress I(V) characteristics for reference DUT sample made on single-crystal 4H-SiC wafers. Image used courtesy of Bodo’s Power Systems [PDF]

Figure 7 shows the box plots of ∆V_f from pre- to post-stress conditions for all samples tested on both types of substrates. In the case of devices made on single-crystal 4H-SiC wafers, the ∆V_f is around 500 mV with an outlier sample at more than 2 V. Devices made on SmartSiC engineered substrates do not present any significant evolution of the forward characteristics, with a ∆V_f around 10mV, close to the measurement accuracy. Only one SiC-engineered substrate sample, out of the ten stressed, shows a significant drift of around 200 mV. These results confirm, at the device level, the first indications of immunity to bipolar degradation of engineered substrates previously obtained at the wafer level.

Figure 7. Box plots showing ∆Vf (Vf shift) for all samples tested for both type of substrates. Image used courtesy of Bodo’s Power Systems [PDF]

Failure analyses are currently being conducted to check the evolution of Shockley stacking faults (SSF) through photoluminescence (PL) after the diodes' electrodes are removed. Detailed results will be presented during PCIM 2025 (SiC Reliability poster session, May 6th, 2025 afternoon).

Experimental Results and Conclusions

Results from the experiments carried out at the device level are in complete agreement with those obtained at the wafer level at high fluences of UV light up to 10 kW/cm² on epitaxial substrates. In the case of the present work, stress was generated on 1200 V SiC PiN diodes through the injection of a forward current of 45 A, corresponding to a current density of 2250 A/cm².

The conclusions from this work obtained on PiN diodes can be extrapolated to the behavior expected in SiC MOSFETs, as the bipolar degradation phenomena observed on these devices originate from the bipolar forward conduction of their body diode.

The study presented here provides irrefutable proof of the ruggedness of SmartSiC engineered substrates against bipolar degradation, contributing to higher performance and more reliable power applications.

The work necessary to obtain the results presented here has been carried out within the TRANSFORM project, with funding from the Key Digital Technologies Joint Undertaking under Grant Agreement No. 101007237.

This article originally appeared in Bodo’s Power Systems [PDF] magazine.