Technical Article

Increasing Power Density Consider Packaging and Silicon

January 28, 2020 by Neil Massey

This article features Nexperia's LFPAK package family designed to improve power density.

Alternately, in server farms where every square meter costs money, commonly we are seeing requests to double the amount of output power in the same power supply housing every 18 months.

If discrete semiconductor suppliers are to meet the challenge, they can no longer simply concentrate on improving the silicon technology, they must also look to improve package performance at the same time. Nexperia, the leader in discrete and MOSFET components and analog and logic ICs headquartered in the Netherlands, has pioneered full copper clip die mounting technology inside the power package (LFPAK Loss-free Package) in order to realize many technical benefits (current capability, RDSon, thermal characteristics etc).


LFPAK Package Family Designed for Power Density 

The LFPAK family of packages is used to improve power density. Its main feature is the use of a full copper clip inside the package and short gull-wing leads on the outside. Nexperia first introduced the package in 2002 with the LFPAK56 package - a power SO8 footprint (5mm x 6mm) that was designed to replace the larger DPAK package. Now, the company has a full range of sizes in both single and dual MOSFET configurations covering a wide range of applications. Most recently, Nexperia released LFPAK88, an 8mm x 8mm package designed for higher power applications that replaces the larger D²PAK and D²PAK-7 packages.


LFPAK discrete MOSFET family of packages

Figure 1: LFPAK discrete MOSFET family of packages


Clip-bond vs. Wire-bond Packages: Power Density Benefits

LFPAK devices are smaller than the older D²PAK and D²PAK-7 parts they replace, delivering an immediate improvement in power density.


LFPAK88 smaller footprint benefit over D²PAK

Figure 2: LFPAK88 smaller footprint benefit over D²PAK


Figure 2 shows the relative footprint sizes of LFPAK88 devices which are 60% smaller than D²PAK parts; also LFPAK88 parts feature a reduced height, giving an overall volumetric reduction of 86%. However, the major difference that enables performance and power density improvements is the use of copper clip technology unlike the older wire-bond technology used within packages like D²PAK and D²PAK7.


LFPAK88 with copper clip and D²PAK with wire-bond connections

Figure 3: LFPAK88 with copper clip and D²PAK with wire-bond connections


Copper clip technology performance benefits include:

1. Current (Amps)

Wire bonds are the limiting factor that determines the amount of current the device can handle. In the case of the D²PAK the maximum diameter of bond wires used is 500µm (due to connecting T-post size).

The largest die that Nexperia can fit into the D²PAK using its latest Trench 9 super-junction 40V silicon is 120A. However, for the smaller LFPAK88 which has no limiting bond wires, the largest die Nexperia can currently include is rated at 425A - in future when the company releases larger silicon, the current rating will be even higher. [Note: the values shown are from measurement and not theory]


2. RDS(on) [in mΩ]

The three 500µm diameter bond wires used in the D²PAK add to the overall RDS(on) of the MOSFET.

For example, using the same Trench 9 40V technology platform in both devices (as above), the largest silicon die Nexperia can fit inside a D²PAK has an RDS(on) of 1.2mΩ. This reduces to 0.7mΩ with the smaller clip bonded LFPAK88 thanks to the elimination of the bond wire resistance. [Note: a 0.55mΩ LFPAK88 part is in development on the T9 platform].


3. Parasitic Source Inductance (nH)

Parasitic source inductance must be overcome at every switching event, as it reduces efficiency. This loss assumes greater significance in applications that need to switch at higher frequencies such as DC/DC converters.Source bond wires also add to the overall parasitic source inductance, and a combination of the longer legs of the D²PAK and the source bond wires give a value of 5nH. By comparison, the LFPAK88 has no source bond wires and has only small gull-wing leads, therefore the impedance is low at 1nH.


4. Current/thermal hotspots

When a high current flows through a device, it is concentrated at bottlenecks where the bond wires connect to the silicon. These current hotspots can lead to thermal/quality issues.

With the LFPAK88, the top copper clip covers significantly more areas so hot spots do not occur.


Simulation of D²PAK and LFPAK88 current density and hotspots on wire-bond

Figure 4: Simulation of D²PAK and LFPAK88 current density and hotspots on wire-bond


Thermal Resistance Rth(j-mb) (K/W)

The LFPAK88 has good thermal performance compared to older packages. For example, if we look at the thermal resistance from the silicon to the bottom of the package where it attaches to the printed circuit board (Rth_Junction to mounting base), then lower resistance values are better.

D²PAK largest die was measured at 0.43K/W; LFPAK88 measured at 0.35K/W.

The better Rth value is mainly resulting from the shorter thermal route with a thinner drain copper clip (0.5mm for LFPAK88 and 1.3mm for D²PAK)


D2PAK and LFPAK88 thinner drain tab

Figure 5: D2PAK and LFPAK88 thinner drain tab


Power Density >1W/mm³

The size benefits, with the increased current capability and better RDS(on) all combine to give a better power density, as summarized in the table (using the same technology platform to give like-for-like performance)


Silicon Autimotive T9 40V Automotive T9 40V
Type BUK7S0R7-40H BUK761R2-40H
Volume x*y*z mm³ 8mm*8mm*1.7mm =108.8mm³ 10.3mm*15.8mm *4.5mm=732.3mm³
Power I²R = W (425A)² * 0.7mΩ = 126.4W (120A)² * 1.2mΩ = 17.3W
Power Density W/mm³ 126.4/108.8 = 1.16 W/mm³ 17.3/732.3 = 0.024 W/mm³
LFPAK88 vs D²PAK 48x better power density  



In conclusion, the drive for power density means that not only are silicon improvements are needed, but also new package construction techniques must be utilized to get the most out of the discrete MOSFETs. The LFPAK full copper clip family of packages enhances the performance of the silicon and is an enabler of reduced footprint and improved power output.


About the Author

Neil Massey is the Internation Product Marketing Manager of Nexperia. He graduated from Staffordshire University specializing in electronic semiconductors. He is experienced in marketing a variety of power discretes and SMPS controllers.


This article originally appeared in the Bodo’s Power Systems magazine.