ON Semi Launches Cost Competitive 0.18 Micron CMOS Manufacturing Process For Digital & Mixed-Signal ASICs

October 01, 2009 by Jeff Shepard

ON Semiconductor has expanded its custom foundry capabilities with the launch of a new industry compatible 0.18 micron (µm) CMOS process technology. The company describes the ONC18 process is an ideal platform for developing low power and highly integrated digital and mixed-signal application-specific integrated circuit (ASIC) devices for automotive, industrial and medical applications. The ONC18-based solutions will be manufactured at ON Semiconductor’s 8-inch wafer fabrication facility in Gresham, Oregon, so the process is also expected to prove attractive for designers of U.S. military applications seeking domestic production with ITAR-compliant partners.

"ONC18 will allow designers in the automotive, industrial, medical and military sectors to develop integrated, low-power digital and mixed-signal ASICs quickly and cost-effectively," said Rick Whitcomb, General Manager and Director for ON Semiconductor’s custom and foundry division. "The ’on-shore’ nature of the fabrication will be particularly useful for U.S. military customers, while planned developments for the process further underline ON Semiconductor’s commitment to the custom foundry business."

Suitable for ASICs requiring up to 10 M gates, the ONC18 process features between four and six levels of metal and allows designers to integrate 1.8V core voltage with 1.8 and 3.3V input/output (I/O). Components for mixed signal design include a variety of resistors and nominal and high value (2.0 fF/µm²) stackable metal-insulator-metal (MIM) capacitors. This base process supports an extensive and modular 0.18 micron BCD, and high voltage roadmap.

ON Semiconductor’s new process is supported with a design kit offering comprehensive core, I/O and memory libraries. Gate densities and power consumptions for high density core and mixed-signal core cells are 124 K gates/mm² and 46 microwatt per megahertz per gate (µW/MHz/gate) and 120 K gates/mm² and 28 µW/MHz/gate, respectively. Memory options include 1.1 M bit synchronous single port and 512K bit dual port SRAM and 1.1M bit high-density, low-leakage VIA-programmable ROM. Future development for the ONC18 platform will enable ON Semiconductor to launch enhanced mixed-signal capabilities and options for higher voltage handling.

The new process design methodology is compatible with common digital and analog/mixed-signal CAD tools, including those from Cadence®, Synopsys® and Mentor Graphics®. ON Semiconductor specialty services, such as advanced die stitching and shuttle services for prototyping, are also available for ONC18-based designs.