Ericsson Shows How Dynamic-Bus Architecture Saves Energy in Datacenters
Ericsson has laid out its vision to system architects developing equipment for computing-intensive environments such as datacenters. The increasing demand for more Internet services and cloud computing is driving both the expansion and building of new datacenters around the world. A key challenge for operators is the minimization of energy expenditure at the board level. Ericsson believes that a significant aid to this process is the use of advanced Dynamic Bus Voltage architectures. This vision was presented by Ericsson at last month's Electronics Goes Green (EGG) congress in Berlin.
Today, the standard power architecture increasingly being used is the Intermediate Bus Architecture (IBA), which uses intermediate bus converters (IBCs) to convert a traditional 48 VDC distribution-level power line used in telecoms to typically a static 12 VDC. This first "down-conversion" 12V level feeds a number of DC/DC point-of-load (POL) regulators, which supply the final load voltages at a chip's logic supply levels of 3V or below. The choice of 12 VDC has been made to ensure a high enough voltage to deliver all the power required by the board, or load, in times of high data traffic. However, this approach becomes highly inefficient when the traffic demand is low.
The Dynamic Bus Voltage is an evolution of the Intermediate Bus Architecture and provides the possibility to dynamically adjust the power envelope to meet load conditions. It achieves this by adjusting the intermediate bus voltage, previously the 12 VDC fixed bus voltage, via the use of advanced digital power control and optimized hardware combined with an energy-optimizer series of algorithms. This can lead to reductions in both energy consumption and power dissipation, which in turn contributes to a reduction in the amount of cooling that is required.
"Dynamic Bus Voltage is a technology that makes possible to reduce board power consumption from anywhere between 3 and 10 percent, depending on the board application," said Patrick Le Fèvre, Marketing and Communication Director, Ericsson Power Modules. "The potential for energy saving is a very substantial one, especially when taking into account the fact that 1W saved at the board level can result in a 3W saving at the power grid level."
Ericsson 3E* BMR456-DBV and BMR457-DBV Advanced Bus Converters offer unprecedented performance and flexibility to system architects developing equipment for information and communication technologies (ICT) requiring smart and efficient board power solutions. Both of these products feature the "Ericsson DC/DC Energy Optimizer firmware" implemented in ARM microprocessor technology which enables a significant contribution to the reduction of power consumption. Hardware and firmware optimized to meet the demands of the Dynamic Bus Voltage (DBV) power architecture, the output voltage of the quarter-brick BMR456-DBV can be adjusted within an operation range of 13.0V to 8.2V, and with the full benefits of the Ericsson DC/DC Energy Optimizer technology, but furthermore adjusted down to 4V to power ultimate below 5V Sleep Mode configuration, which today requires an extra power-module.
Designed for smaller systems, the eighth-brick-format BMR457-DBV full operational output voltage is optimized to deliver high performance from 13.2V to 8.2V and can be adjusted down to 6.9V making it possible to power the mid-power range of applications requiring 6V Sleep Mode configuration. In both products, the output voltage can be adjusted via PMBus commands or preset profiles stored by the system designer in the built-in USER_STORE memory block, making it simple to adjust the intermediate board bus voltage to a level that will guarantee the lowest power consumption.
In addition, embedding industry-first technology and Ericsson IP, the Ericsson DC/DC Energy Optimizer not only permanently optimizes switching parameters to reduce energy consumption, but also offers a large number of features including the ability to handle input voltage transients with slew-rates up to 0.5 V/µs, while keeping the output voltage within +/-10 percent. This ensures that the output voltage does not trigger over-voltage protection. It also very efficiently manages pre-bias start-up operation and shut down is fully controlled avoiding voltage spikes that cause avalanche conditions in the secondary-side synchronous rectification MOSFET, making a contribution to further improve reliability.
