AI Datacenter Grid-to-Core Power Architecture

This article is published by EEPower as part of an exclusive digital content partnership with Bodo’s Power Systems.

The rapid escalation of computing workloads—driven by AI—is pushing power requirements to grow at an unprecedented rate, exceeding 50% CAGR from 2024 to 2028. This surge is propelling power consumption into the hundreds of gigawatts and forcing the industry to accelerate platform development cycles, now releasing new servers every 12–15 months rather than the traditional 30 month cadence.

Power demand at the AI SoC (xPU) level is rising especially sharply, surpassing multiple kilowatts for devices entering production in early 2026. This AI era “Moore’s Law” of parallel processing is effectively doubling power needs yearly, far outpacing historical growth trends.

Image used courtesy of Adobe Stock

At the rack level, this creates a need for a fundamentally different powerdistribution approach capable of supporting much higher load levels. For instance, current Nvidia Blackwell-based NVL72 racks consume around 130 kW, but the next generation is expected to reach roughly 300 kW.

With Rubin-based NLV144 systems likely to double GPU density and future NVL576 configurations nearing 1 MW per rack, raising distribution voltage becomes essential to reduce losses. This drives the shift from the long-standardized 48 V OCP bus to an 800 V DC bus, distributed using two wires—or eventually a ±400 V system plus earth (Fig.1).

As power in the compute rack increases and proliferates across the datacenter, it is no longer practical to place the AC/DC stage inside the same rack. A new dedicated “SideCar” rack is emerging to convert incoming 415 Vac to 800 V DC. This 415 Vac distribution originates in the datacenter PDU, passes through the AC UPS, and is fed by a 480 Vac supply from the main switchboard tied to the mediumvoltage grid (13.8–35 kVac).

Figure 1. Next-generation Grid to Core Datacenter Architecture. Image used courtesy of Bodo’s Power Systems [PDF]

The industry—from OEM reference designs to hyperscaler-driven ODM redesigns and power supply manufacturers—is collectively transitioning to this new architecture. Hybrid and legacy approaches will persist temporarily, including racks that still accept AC input and generate 800 V for smaller GPU counts, but the ecosystem is converging toward a standardized model aligned with OCP initiatives.

Within the compute rack, existing infrastructure still relies on 48 V, necessitating highly efficient, high-density converters to step down from 800 V. Renesas contributed to a 6 kW reference design for a 12 kW blade architecture built on 650 V GaN FETs in TOLT packaging and 80 V MOSFETs in 5×6 mm QFNs. Using a DTX unregulated LLC topology switching above 900 kHz, the design achieves over 98% peak efficiency and more than 2.5 kW/in³ power density. Like all Renesas PoCs, this includes full schematics, layout, BOM, and test data.

Below 48 V, the architecture remains mostly unchanged for now. However, soaring SoC load currents—approaching 4 kA—require new delivery methods (Fig.3 and 4). Traditional lateral power routing is no longer sufficient. Vertical Power Delivery (VPD) is emerging, achievable through compact high-phase-count power stages or by integrating inductors in 3D structures.

Renesas supports this with fully digital multiphase controllers offering multiprotocol interfaces, up to four control loops, and top-tier transient performance with TLVR. Complementing these are Smart Power Stage modules delivering up to 100 A peak per phase, available in combined multiunit packages or integrated 3D structures enabling phasedense VPD solutions reaching 2 A/mm² current density.

These are backed by an end-to-end ecosystem including pre-layout simulations, PDN analysis, hardware tools, interposers, tuning, measurement, and validation methodologies. More advanced modular solutions are in development, incorporating additional conversion stages while still enabling VPD—leveraging innovations like IVR for faster switching and high-bandwidth last-stage regulation.

One important architectural discussion concerns the future of the intermediate 12 V rail currently derived from 48 V using a 4:1 IBC (Fig.2). To improve efficiency and current density in the final multiphase stage—especially when using advanced low-voltage silicon nodes—this intermediate voltage may be reduced.

Renesas offers high-performance Hybrid Switched-Capacitor (HSC) converters exceeding 98% efficiency. Using an 8-switch design, these can produce 6 V at peak efficiencies up to 97%, depending on the regulation approach. Renesas has also released reference designs for this conversion.

Alternatively, a multiphase buck using 100 V GaN can raise switching frequency to significantly shrink converter size. Renesas has demonstrated 48 V solutions delivering up to 3 kW with nearly 1 kW/in³ density, operating in 8-phase mode down to 6 V or 4-phase mode at 12 V with digitalcontrol flexibility.

Figure 2. New AI Compute Rack Architecture Evolution Examples. Image used courtesy of Bodo’s Power Systems [PDF]

Further architectural optimizations are expected as the 800 V distribution model matures. The internal 48 V bus within the xPU blade could be eliminated entirely, replaced with direct high-ratio conversion similar to existing 16:1 stages. Renesas has created a 6 kW, 800 Vto12 V (64:1) reference design using DTX topology, scalable toward the much higher power levels—potentially around 20 kW— anticipated for future AI blades as xPU consumption continues to rise.

Figure 3. AI Compute Trays Power Delivery Examples. Image used courtesy of Bodo’s Power Systems [PDF]

GaN technology remains a crucial enabler across these high-density power stages. Its widebandgap characteristics are accelerating powercontent growth in datacenters faster and more dramatically than SiC in many segments, particularly where GaN can substitute for silicon MOSFETs. As GaN evolves toward lower-voltage, higher-performance operation, its penetration into near-core power delivery will expand, boosting density without sacrificing efficiency.

In AC/DC sidecar racks—currently dominated by 1200 V SiC devices—an emerging element is the 650 V bidirectional GaN switch. This nearly ideal four-quadrant switch enables single-stage topologies and simplifies frontend architectures like T-type or Vienna rectifiers. It reduces density and cost by replacing traditional back-to-back device configurations.

Figure 4. New AI Compute Rack SoC Supply Evolution Examples. Image used courtesy of Bodo’s Power Systems [PDF]

High-voltage SiC devices (>1.2 kV) will play an important role in solid-state transformer (SST) systems, where medium-voltage AC from the grid enters the datacenter power room and is converted directly into 800 V DC for hall-level distribution. This SST-based approach eliminates bulky transformers, switchgear, and PDUs, dramatically cutting copper usage because 800 V DC cables can carry roughly 1.5× the power of 415 Vac cables.

Another significant development is the shift in energystorage architecture from AC-based diesel backup toward distributed 800 V DC storage integrated into the data center environment. High-power capacitor or supercap systems positioned near compute racks will support short-duration energy needs, incorporating bidirectional DC/DC converters, controllers, and drivers to manage power flow. At the facility level, MV battery storage and onsite backup generation will become essential to ensuring the continuous operation of AI-focused datacenters.

Resources:

• https://developer.nvidia.com/blog/building-the-800-vdc-ecosystem-for-efficient-scalable-ai-factories/
• https://developer.nvidia.com/blog/nvidia-800-v-hvdc-architecture-will-power-the-next-generation-of-ai-factories/
• https://www.renesas.com/en/about/newsroom/renesas-powers-800-volt-direct-current-ai-data-center-architecture-next-generation-power

This article originally appeared in Bodo’s Power Systems [PDF] magazine.