Darnell’s Intel on APEC

March 05, 2007 by Jeff Shepard

Analyzing the papers presented at the annual IEEE Applied Power Electronics Conference (APEC) often provides interesting market intelligence, or ‘intel,’ as it is sometimes called. As Darnell Group completed our analysis of the APEC 2007 technical papers, Intel indeed stood out. Over the past 5 years (2002-2006), Intel authored a total of 4 papers. At this year’s APEC, researchers from Intel were listed as authors on 6 papers. Quite a change.

Five of the six papers present an interesting "package" of technologies, design approaches, and pending patents. "A 100 MHz Eight-Phase Buck Converter Delivering 12A in 25mm² Using Air–Core Inductors," presented a voltage regulator (VR) chip manufactured using a 90 nm CMOS process. The resulting IC was mounted on a flip–chip package together with surface–mount inductors and decoupling capacitors. This 2.5mm high VR delivered a "record breaking" (according to the authors) power density of 3.78 kW/in³. The VR supported load changes between 5A and 10A with <100ps rise times and delivered a measured efficiency of 79.3% – 84.0% for output voltages of 1.2–1.5Vdc. This is certainly an interesting VR design.

Several of the other papers presented additional insights (and a few patent disclosures). "Performance Analysis of Trench Power MOSFETs in Synchronous Buck Converter Applications" investigated several trench MOSFET technologies using mixed–mode device/circuit modeling. Individual power loss contributions from the control and synchronous MOSFETs and their dependence on switching frequency between 500 kHz and 5 MHz were discussed in detail. This information will be valuable when implementing the patent pending adaptive FET modulation schemes discussed in "Analysis and Design of Voltage Regulator with Adaptive FET Modulation to Improve Efficiency."

Adaptive FET modulation (AFM) operates at a fixed switching frequency over almost the whole load range and enables the design of VRs that achieve high efficiency under both heavy and light loads. "The capability of adaptive modulation of FETs parasitic charges and resistances along with adaptive gate driving voltage allows achieving the best FET optimization over a wide loads range," the authors concluded. Later in this year’s APEC, two of the authors of this paper presented a second paper titled, "Adaptive Controller with Mode Tracking and Parametric Estimation" (also with a patent pending notice).

This second AFM paper presented digital controller algorithms that allow detecting discontinuous conduction mode (DCM) and continuous conduction mode (CCM) operations without instantaneous or cycle–by–cycle sensing and sampling of inductor current. All that is needed is sensing the converter input current to detect DCM and CCM modes for variable frequency operation and to estimate peak inductor current. "The knowledge of such predicted and estimated information opens the door for easier implementation of control schemes such as light load efficiency and performance improvement schemes, current mode control and automatic and online power stage self design," the authors concluded.

The final paper in the ‘sequence’ presented "Novel Current Sharing Schemes for Multiphase Converters with Digital Controller Implementation" (with yet another patent pending notice). Two current sharing schemes were presented, resulting in several current sharing and online calibration schemes. Both concepts share the fact that their current sharing accuracy is not a function of sensing accuracy and therefore are immune to component parasitics and aging. They do not necessarily require current sensing and current comparison for each phase they are based on efficiency maximization or loss minimization.

Rounding out the six papers authored or co–authored by Intel researchers was "390V Input VRM for High Efficiency Server Power Architecture." This isolated 390V to 3.3V dc–dc converter fits into a standard VRM form factor and could also find use as a bus converter in an intermediate bus power architecture. This paper focused on opportunities for improving system–level energy efficiencies. Commenting on the potential for using a high–voltage distribution bus in servers and other equipment systems, the authors noted: "The converter is a critical building block in a proposed power distribution architecture with a reduced number of conversion stages, which increases overall system efficiency."