New Industry Products

International Rectifier Creates New Accelerator Motor Drive Power-Management Architecture

November 08, 2000 by Jeff Shepard

International Rectifier (El Segundo, CA) has designed a motor drive power-management architecture, positioned between the micro- or DSP-controller and the motor, to enhance and simplify DSP and microprocessor-controlled motion-control circuits. By simplifying motor drive power management, IR hopes that more design effort can be concentrated on the main control algorithm and man-machine interface.

Called the Accelerator, the new chip-set architecture consists of mixed signal 0.5um CMOS and high-voltage ICs with ratings from 600V to 1,200V. This power-management peripheral architecture can be applied to ac induction motors as well as brushless dc motors. Typical applications include industrial ac drives, industrial servo drives, compressor drives, washing machines, electric power steering, integrated starter alternators and high-reliability drives.

The IR peripheral architecture is claimed to simplify power-management design and increase reliability by reducing the total parts count by 25 percent and cutting the circuit-board footprint by 50 percent. Motor drives using this architecture should easily fit within the dimensions of the industry-standard ECONO2 package outline, approximately 4.25" x 1.75" x 0.62".

According to David Tam, vice president for power integrated-circuit products at IR, "The new Accelerator architecture delivers speed range 10 times wider than conventional designs, with significantly improved low-speed operation for ac inverter motor drives by optimizing dead time. System performance is enhanced because the temperature-compensated current-measurement technique enables torque precision as high as plus/minus one percent, versus plus/minus two to three percent in existing motor drives."

This chip set integrates analog and interface functions and features a dual-port memory with a serial interface at I/O. It includes various diagnostic functions, dead-time generation and dead-time compensation functions. The chip can be programmed by a user-defined PWM or a built-in, optional space vector PWM generator.