Market Insights

International Electron Devices Meeting – IEDM 2016

February 04, 2017 by Gary Dolny

This article discusses the 62nd annual IEEE International Electron Devices Meeting that was held in San Francisco, California, USA.

The 62nd annual IEEE International Electron Devices Meeting, (IEDM) was held in San Francisco, California, USA December 3 - 7, 2016. For more than six decades, the annual IEDM has been the world’s largest and most influential forum for technologists to unveil breakthroughs in transistors, integrated circuits, and related micro and nanoelectronics devices. This year more than 1600 engineers and scientists from around the world attended the event which was held at the Hilton San Francisco Union Square.

That tradition continued this year with a few new twists, including a supplier exhibition and a later submission deadline for the final, four-page paper. This streamlined process ensures that as the pace of innovation in electronics quickens, IEDM remains the place to learn about the latest and most important developments. The submission/ acceptance process continued to be highly competitive, with only approximately a third of the submitted abstracts being accepted assuring a high-quality technical program.

“The industry is moving forward at an accelerated pace to match the increasing complexity of today’s world, and a later submission deadline enables us to shorten the time between when results are achieved in the lab and when they are presented at the IEDM,” said Dr. Martin Giles, IEDM 2016 Publicity Chair, Intel Fellow, and Director of Transistor Technology Variation in Intel’s Technology and Manufacturing Group.

Tibor Grasser, IEDM 2016 Exhibits Chair, IEEE Fellow and Head of the Institute for Microelectronics at TU Wien, added, “We decided to have a supplier exhibition in conjunction with the technical program this year, as an added way to provide attendees with the knowledge and information they need to advance the state-of-the-art.” The exhibit was an opportunity for the participants to learn about and interact with key equipment manufacturers and other suppliers.

The conference began with a weekend program of 90-minute tutorials and all-day Short Courses taught by industry leaders and world experts in their respective technical disciplines. These weekend events preceded a technical program of some 220 papers and a rich offering of other events including thought-provoking plenary talks, spirited evening panels, special focus sessions on topics of great interest, IEEE awards and an event for entrepreneurs sponsored by IEDM and IEEE Women in Engineering.

The power semiconductor device community was once again well represented at this year’s IEDM. In addition to a full session of contributed papers power devices were also the subject of one of the conference’s Special Focus sessions entitled the System-Level Impact of Power Devices. The Special Focus session featured a series of invited talks by six experts in the field who detailed the latest developments in wide-bandgap power devices, showed how they are transforming power delivery systems, benchmarked material characteristics and reliability, and considered future directions for the technology.

Wide-bandgap power devices, particularly GaN, received the bulk of the attention in both the contributed papers as well as the focus session. A research group from Panasonic Corp., Japan, described a normally off vertical current flow GaN transistor on a bulk GaN substrate with low specific on-state resistance of 1.0 mω-cm2 and high off-state breakdown voltage of 1.7kV. The novel device structure consisted of P-GaN/GaN/AlGaN layers grown epitaxially on V-shaped trenches etched into the surface of the drift layer. The channel used a so-called semipolar face to reduce carrier density and achieve a threshold voltage of 2.5V. The device demonstrated stable operation and fast switching at 400V/15A [1].

A group from Massachusetts Institute of Technology, USA demonstrated a novel vertical GaN MIS Schottky barrier rectifier with implanted trench field-ring termination. The basic device structure consisted of multiple trenches with MIS structures fabricated along the trench bottoms and sidewalls to achieve a TMBS-type shielding effect. Field limiting rings were formed by Ar implantation into the trench bottoms to further optimize the field distribution while the Scottky contact was formed on the top surface. The reverse leakage current was improved by a factor of over 104 and the breakdown voltage increased from 400 V to 700 V, while the low turn-on voltage (0.8 V) and on-resistance (2 mΩ·cm2) were retained [2].

Another group from Panasonic Corp., Japan, demonstrated a current collapse free GaN gate-injection transistor using a thick buffer layer on a bulk GaN substrate. Because the GaN substrate eliminates lattice and thermal mismatches a much thicker buffer layer (15μm) can be used as compared to the conventional 5μm GaN-on-Si structure. The thicker buffer layer offers a number of advantages including reduced output capacitance to enable fast switching, as well as improved crystal quality to suppress current collapse [3].

A collaboration between the Hong Kong University of Science and Technology, and the Suzhou Institute of Nano-tech, China discussed the use of a LPCVD SiNx gate dielectric for enhancement mode GaNMISFETs. The group utilized a novel interface protection technique, in which a thin layer of low-temperature PECVD-SiN was inserted between the LPCVD SiNx and the GaN surface. The resulting structure displayed greatly improved interface quality and resulted in a highly reliable gate dielectric, a stable Vth of 2.34V, low Rdson and small dynamic Ron degradation [4].

T. Terashima, of Mitsubishi Electric Corp., Japan, discussed the superior performance of SiC power devices and their limitation due to selfheating. He pointed out that although the theoretical on-state resistance of SiC can be two-orders of magnitude lower than an equivalent Si device, the increase of current density by reduced Ron,sp is suppressed to 1/√Ron,sp under the same heat dissipation performance of the packaging. An even more severe limitation is imposed by transient self-heating under short-circuit operating conditions, where the low Ron causes rapid temperature rise. He concluded that to fully realize the benefits offered by the superior performance of SiC, it is necessary to develop high-speed protection circuitry to limit the short circuit event to about 2 μsec, as well as to improve thermal performance of packaging [5].

A research group from the University of Tsukuba, Japan, presented a p-channel SiC MOSFET with high short circuit withstand time capability. The target application was complimentary inverter applications with the goal of reducing circuit deadtime and thereby improving the total harmonic distortion in the output waveform. The device showed 15% higher short circuit energy, improved gate oxide reliability and improved avalanche ruggedness compared to an equivalent n-channel SiC MOSFET. Although on-state resistance was high, several approaches for its reduction were proposed [6].

G. Rescher and his colleagues from Technische Universtat Wein, Austria, reported a hysteresis in the subthreshold current on nchannel SiC MOSFETs due to the presence of border traps. However the voltage shift is fully recoverable when a bias above threshold is applied and does not impact reliability [7].

Although the focus was on wide-bandgap devices silicon IGBTs still maintained a presence. K. Kukishima of Tokyo Institute of Technology, Japan, along with a number of industrial and academic collaborators described a three-dimensional scaling approach to achieve a very low Vcesat IGBT. The scaling is applied to vertical and lateral dimensions as well as to the gate voltage. A significant decrease in on-state voltage, from 1.70V to 1.26 V was experimentally confirmed [8].

The special focus session featured a number of presentations addressing how wide-bandgap devices will impact future power delivery systems. A. Huang of North Carolina State University, USA presented a review of the recent progress in wide-bandgap devices and commented on their potential transformative impacts on low, medium and high-power delivery systems [9], while A. Lidow of EPC Corp. USA, focused on the application of GaN devices in server applications and examined the various tradeoffs involved in converting a 48V bus down to a 1.0V load [10]. Similarly, H. Isheda, of Panasonic Corp., Japan, reviewed the current status of the GaN gate injection transistors for integrated circuits and their application to power switching systems [11]. G. Deboy of Infineon, Germany compared key parameters such as capacitances & switching losses for silicon, SiC and GaN power devices with respect to applications in switch mode power supplies operating from a single-phase AC line. His analysis concluded that silicon devices will prevail in classic hard switching applications at moderate switching frequencies whereas SiC and GaN based power devices will play to their full benefits in resonant topologies at moderate to high switching frequencies [12].

A group from Texas Instruments, USA, investigated the applications reliability of GaN devices. They showed that traditional reliability qualification methodologies may not be adequate for emerging power management technologies because fundamental switching transitions are not covered. They further showed that hard switching using a double-pulse test is predictive of device performance under most system applications and that their experimental devices could pass standard qual and perform well in applications [13].

Finally, H. Ohashi of NPERIC, Japan, addressed an issue that he called an “inconvenient truth”; the efficiency of modern power converters is approaching 100% and thus the target of power electronics progress should change from improved converter efficiency to the overall prevalence of efficient use of energy. To illustrate this, he introduced the concept of “nega-watt cost” where a “nega-watt” (negative watt) is a hypothetical unit of energy that is not consumed either because of efficiency or conservation. The nega-watt cost is minimized by reducing system and operating cost while maximizing energy saving and operating time [14].



  1. D. Shibata, et. al., “1.7 kV / 1.0 mΩ-cm2 normally-off vertical GaN transistor on GaN substrate with regrown p-GaN/AlGaN/GaN semipolar gate structure”, IEDM Technical Digest, Dec. 2016, pp. 248-251.
  2. Y. Zhang et. al., “Novel GaN trench MIS barrier Schottky rectifiers with implanted field rings,” IEDM Technical Digest, Dec. 2016, pp. 252-255.
  3. H. Handa et. al. ”High-speed switching and current collapse free operation by GaN gate injection transistors with thick buffer layer on bulk GaN substrates”, IEDM Technical Digest, Dec. 2016, pp. 256-259.
  4. M. Hua, et. al., “Integration of LPCVD-SiNx gate dielectric with recessedgate E-mode GaN MIS-FETs: toward high performance, high stability and long TDDB lifetime,” IEDM Technical Digest, Dec. 2016, pp. 260-263.
  5. T. Terashima, “Superior performance of SiC power devices and its limitation by self-heating,” IEDM Technical Digest, Dec. 2016, pp. 264-267.
  6. J. Namai, et. al., ”Experimental demonstration of -730V vertical SiC p-MOSFET with high short circuit withstand capability for complementary inverter applications”, IEDM Technical Digest, Dec. 2016, pp. 272-275.
  7. G. Rescher et. al.,”On the Subthreshold Drain Current Sweep Hysteresis of 4H-SiC nMOSFETs”, IEDM Technical Digest, Dec. 2016, pp. 276-279.
  8. K. Kakushima et. al., “Experimental Verification of a 3D scaling principle for low Vce(sat) IGBT”, IEDM Technical Digest, Dec. 2016, pp. 268-271.
  9. A. Huang, “Wide bandgap (WBG) power devices and their impacts on power delivery systems,” IEDM Technical Digest, Dec. 2016, pp. 528-531.
  10. A. Lidow, “System level impact of GaN power devices in server architectures,” IEDM Technical Digest, Dec. 2016, pp. 536-539.
  11. H. Isheda, GaN-based semiconductor devices for future power switching systems,” IEDM Technical Digest, Dec. 2016, pp. 540-543.
  12. G. Deboy et. al., “Si, SiC and GaN power devices: an unbiased view on key performance indicators,” IEDM Technical Digest, Dec. 2016, pp. 532-535.
  13. S. Bahl “Application reliability validation of GaN power devices”, IEDM Technical Digest, Dec. 2016, pp. 544-547.
  14. H. Ohashi, “Horizon beyond ideal power devices”, IEDM Technical Digest, Dec. 2016, pp. 548-551.


This article originally appeared in the Bodo’s Power Systems magazine.