Meeting AI Demands With SiC and GaN Power Supplies

This article is published by EEPower as part of an exclusive digital content partnership with Bodo’s Power Systems.

The rise of artificial intelligence has necessitated a strong growth of processing power in data centers. As shown in Figure 1, Infineon predicts a single GPU’s power consumption to rise exponentially, reaching approximately 2000 W by 2030 with an AI server rack peaking at an astounding >300 kW. These demand new architectural changes in AC and DC distribution systems of data center racks, focusing on reducing conversion and distribution power losses from grid to core.

Image used courtesy of Adobe Stock

Figure 2 (right) shows an example diagram of an Open Compute Project (OCP) rack-power architecture. Each power shelf is fed by a three-phase input and houses multiple PSUs; each PSU is fed by a single-phase input. The rack outputs a DC voltage (e.g., 50 V) to the bus bar, which also connects to IT and battery shelves.

The AI trend mandates a power evolution for the PSU, as shown in Figure 2 (left). Let's walk through each of these PSU generations with an example of the implementation topology and device technology recommendations.

Trends and Power Evolution for AI Server Rack PSUs

First-generation AI PSUs: Increased power with the same architecture, ~5.5–8 kW, 50 V_out, 277 V_ac, single-phase

The present generation of PSUs for AI servers mostly follows the ORv3-HPR standard. In this standard, most specifications, including input and output voltages and efficiency, are unchanged compared to the preceding ORv3 3 kW specification. However, it has updated specifications related to AI-server requirements, such as higher power and peak power requirements (described later) and the narrower output voltage regulation due to the modified communication with the BBU shelf.

Although each power shelf is fed by a three-phase input (400–480 V_ac L-L), as shown in Figure 2, the input for each PSU is single-phase (230–277 V_ac). Figure 3 shows an example implementation of first-generation PSUs to meet the ORv3-HPR specifications: the PFC stage can be two interleaved totem-poles using CoolSiC MOSFETs 650 V for the fast legs and 600 V CoolMOS SJ MOSFETs for the slow leg. The DC-DC stage can be a full-bridge LLC using CoolGaN Transistors 650 V, whereas the secondary full-bridge rectifier and ORing are with OptiMOS power MOSFETs 80 V. Also shown in this example is the middle stage, named “hold-up time extension” or “baby boost,” the function of which is to reduce the size of the bulk capacitors. It consists of a boost converter discharging the energy-storage capacitor to regulate the LLC input voltage during the line-cycle-dropout event. During normal operation, this boost converter is idle and is bypassed by a low ohmic 600 V CoolMOS SJ MOSFET.

Figure 1. Electricity demands of x86 and Arm-based server CPUs compared with GPUs and TPUs. Image used courtesy of Bodo’s Power Systems [PDF]

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Figure 2. Power evolution for AI server PSUs (a). Example of a server rack architecture (b). Image used courtesy of Bodo’s Power Systems [PDF]

Figure 3. First-generation AI PSU topology and an example of device technology. Image used courtesy of Bodo’s Power Systems [PDF]

Figure 4. Second-generation AI PSU topology and an example of device technology. Image used courtesy of Bodo’s Power Systems [PDF]

Second-generation AI PSUs

Increased line voltage for a higher power of ~8–12 kW, 50 V_out, 277–347 V_ac, single-phase

With the aforementioned rack power increasing to >300 kW, the density of power shelves becomes crucial. Therefore, the next generation of PSUs is going towards 8 kW and up to 12 kW in a singlephase architecture. As the power per rack is higher, the number of racks in a data center may, in some cases, be constrained by the distribution current rating and losses. Therefore, in an attempt to reduce the AC distribution current and losses, some data centers may increase the AC distribution voltage to the rack from 400/480 V to 600 V_ac L–L (three-phase), where the PSU input voltage increases from 230/277 V_ac to 347 V_ac (single-phase).

Although this change can benefit the data center’s operation and utilization, it can impact the PSU voltage ratings and design. At 347 V_ac input, the PFC output must be set to ~575 V_dc, implying that 650 V devices are insufficient in voltage rating. Figure 4 shows an example implementation: the two-level totem-pole PFC discussed in first-generation PSUs can be replaced by a three-level flying-cap totem-pole PFC (3-L FCTP PFC) stage using the CoolSiC MOSFETs 400 V. The concept of a multi-level power conversion allows for a higher input voltage while using switches with a lower voltage rating. 3-L FCTP PFC offers higher efficiency and power density benefits due to the frequency multiplication effect of multi-level topologies. Most importantly, optimizing the CoolSiC technology for a lower breakdown voltage of 400 V results in an excellent FoM compared to CoolSiC 650 V and 750 V reference devices, as shown in Figure 5 (left). Additionally, Figure 5 (right) shows a plot of the on-state resistance across the temperature range, showing that R_DS(on) 100°C for CoolSiC MOSFET 400 V is only 11% higher than R_DS(on) 25°C. The benefit of such a flat R_DS(on) vs. Tj characteristic is that it enables CoolSiC MOSFETs with higher R_DS(on) typ, resulting in better cost and switching performance.

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Figure 5. Improved switching FoMs and stable R_DS(on) dependence on junction temperature for CoolSiC 400 V vs. 650 V and 750 V: Figure of merit (a), R_DS(on) vs. T_j (b). Image used courtesy of Bodo’s Power Systems [PDF]

Three-phase LLC topology is a good choice for the DC-DC stage, with CoolSiC MOSFETs 750 V for primary-side switches and OptiMOS 5 power MOSFETs 80 V for the secondary full-bridge rectifier and ORing. This solution can deliver a higher power due to the third half-bridge switching leg, offering output current ripple cancellation and automatic current sharing to the inherent coupling between the three switching half-bridges.

Third-generation AI PSUs

Three-phase architecture and 400 V distribution for the highest power of ~22 kW 400 Vout 480–600 Vac three-phase

For further increase in rack power, the third generation of AI PSUs will have a more disruptive rack architecture, as follows:

• PSU input change from single-phase to three-phase to improve density and cost
• Power-shelf PSU output voltage increase from 50 V to 400 V to reduce the bus bar current, losses, and cost

Figure 6 shows an example implementation of a three-phase input and a 400 V output PSU with recommended devices and technologies. The PFC stage is a Vienna converter, a popular topology for three-phase PFC applications. Its key advantage is that it allows the use of 650 V devices because of its split bus voltages, using twice the number of back-to-back CoolSiC MOSFETs 650 V and CoolSiC 1200 V diodes. Since the PFC output is a split capacitor, each capacitor voltage is 430 V and feeds a full-bridge LLC converter with CoolGaN Transistors 650 V on the primary and secondary sides. The two LLC stages are series-connected on the primary side and parallel-connected on the secondary side to feed the 400 V bus bar.

Figure 6. Third-generation AI PSU topology and an example of the device technology. Image used courtesy of Bodo’s Power Systems [PDF]

Alternatively, the two back-to-back CoolSiC MOSFETs 650 V can be replaced by the CoolGaN bidirectional switch (BDS) 650 V, which is a true normally-off monolithic bidirectional switch. This means that a single CoolGaN BDS can replace four discrete power switches for the same R_DS(on) due to its highly effective die-size utilization in terms of R_DS(on)/mm².

WBG Benefits for AI PSUs

Wide-bandgap (WBG) semiconductors, such as CoolGaN, become the optimal choice for AI PSUs as they offer the best efficiency at higher switching frequencies, enabling higher power density converters without compromising conversion efficiency.

Aside from the significant nominal-power rise of the AI PSU, the GPU draws a higher peak power and generates high load transients, as shown in Figure 7. Therefore, the DC-DC stage output must be dynamic enough while the voltage overshoot and undershoot must stay within the specified limits. The DC-DC stage output dynamics can be increased by raising the switching frequency, thereby increasing the control loop bandwidth.

Figure 7. AI PSU peak power demanded by AI GPUs. Image used courtesy of Bodo’s Power Systems [PDF]

CoolGaN devices easily address this requirement of a higher switching frequency due to their superior FoM and lowest switching losses among Si, SiC, and GaN devices. Especially in soft-switching LLC converters, CoolGaN has the lowest output capacitor charge (Qoss), which plays a vital role in reaching ZVS (zero voltage switching) more easily. Subsequently, this facilitates a more precise dead-time setting and thus eliminates unnecessary dead-time conduction losses.

 3-L Flying-Cap Totem-Pole PFC

Three-level flying-cap totem-pole PFC (3-L FCTP PFC) using CoolSiC MOSFETs 400 V not only allows higher AC input voltage as discussed in Section 2.2 but also offers higher density and efficiency benefits due to the excellent figure of merit (FoM) compared to the CoolSiC 650 V and 750 V reference devices. The optimized inductor design (size, material, and winding) and choice of R_DS(on) in a 3L-topology with reduced switching losses help achieve a flat efficiency curve with a peak efficiency >99.3% and a full-load efficiency >99.15%, as shown in Figure 8.

Figure 8. Efficiency comparison: 3-L FCTP PFC vs. 2-L TP PFC. Image used courtesy of Bodo’s Power Systems [PDF]

Takeaways

The race to deploy new technology to cater to the demands of AI applications in data centers has already started, creating a surge in rack and PSU power demand. The power demand for AI PSUs is growing from 3-5.5 kW to 8-12 kW single-phase and up to 22 kW three-phase. This demand challenges data center operators in optimizing the efficiency and utilization of data center space and available power. Addressing these challenges leads to new rack architectures and AC-DC distribution configurations, positioning designs based on CoolSiC and CoolGaN at the forefront of PSU design for the best efficiency and power density.

Moreover, new WBG devices can enable the best cost-to-performance ratio for new topologies, as explained in the use of CoolSiC MOSFETs 400 V in the 3-level flying-cap totem-pole PFC or the CoolGaN BDS 650 V in the three-phase Vienna PFC.

Finally, Infineon’s wide portfolio of all power device technologies (Si, SiC, and GaN) and optimized gate-driver ICs support today’s and next-generation platforms and trends with a hybrid approach. It leverages three technologies, allowing the PSU design to reach the best flexibility and achieve a trade-off between efficiency, power density, and system costs. Moreover, Infineon pioneers advancements, such as the world’s first 300 mm power GaN technology, which will further aid the futuristic designs.

This article originally appeared in Bodo’s Power Systems [PDF] magazine.