Testing Gallium Nitride Devices Under Extreme Voltage and Current Stress
This article focuses on the stressor of current. Parts were tested to failure under two specific conditions that demonstrate the exceptional robustness of eGaN FETs.
Standard qualification testing for semiconductors typically involves stressing devices at-or-near the limits specified in their data sheets for a prolonged period of time, or for a certain number of cycles, with the goal of demonstrating zero failures. By testing parts to the point of failure, an understanding of the amount of margin beyond the data sheet limits can be developed, but more importantly, an understanding of the intrinsic failure mechanisms of the semiconductor can be found.
By knowing the intrinsic failure mechanisms, the root cause of failure, and the device’s behavior over time, temperature, electrical or mechanical stress, the safe operating life of a product can be determined over a more general set of operating conditions .
Stressors and Intrinsic Failure Mechanisms
The key stress conditions for all power transistors involve voltage, current, temperature, and humidity as listed in Table 1.
Table 1: Stress Conditions and Intrinsic Failure Mechanisms for eGaN® FETs
By stressing devices with each of these conditions to the point of generating a significant number of failures, an understanding of the primary intrinsic failure mechanisms for the devices under test (DUT) can be determined. To generate failures in a reasonable amount of time, the stress conditions typically need to significantly exceed the data sheet limits of the product.
This article focuses on the stressor of current. Parts were tested to failure under two specific conditions that demonstrate the exceptional robustness of eGaN FETs; (1) Safe Operating Area (SOA), where eGaN FETs are exposed simultaneously to high current (ID) and high voltage (VDS) for a specified pulse duration; and, (2) short circuit withstand time, where eGaN FETs are subjected to a short circuit with the gate turned on up to its maximum voltage.
Safe Operating Area
The primary purpose of SOA testing is to verify the FET can be operated without failure at every point (ID, VDS) within the data sheet SOA graph. It can also be used to probe the safety margins by testing to fail outside the safe zone.
During SOA tests, the high-power dissipation within the die leads to a rapid rise in junction temperature and the formation of strong thermal gradients. For sufficiently high power or pulse duration, the device simply overheats and fails catastrophically. This is known as thermal overload failure. In Si MOSFETs, another failure mechanism, known as secondary breakdown (or Spirito effect ), has been observed in SOA testing. This failure mode, which occurs at high VD and low ID, is caused by an unstable feedback between junction temperature and threshold VTH.
Figure 1: EPC2034C SOA plot. “Limited by RDS(on)” line is based on data sheet maximum specification for RDS(on) at 150 °C. Measurements for 1 ms (purple triangles) and 100 µs (green dots) pulses are shown. Failures are denoted by red triangles (1 ms) or red dots (100 µs).
Figure 1 shows the SOA data of a 200 V EPC2034C. In this plot, individual pulse tests are represented by points in (ID,VDS) space. These points are overlaid on the data sheet SOA graph. Data for both 100 µs and 1 ms pulses data are shown together. A broad area of the SOA was interrogated without any failures (all green dots), ranging from low VDS all the way to VDS;max (200 V). All failures (red dots) occurred outside the SOA, indicated by the green line in the data sheet graph. The same applies to 1 ms pulse data (purple and red triangles): all failures occurred outside of the data sheet SOA.
Figure 2 compares SOA data between a commercial power MOSFET (dotted lines) and an EPC2045 eGaN FET (solid lines) with a similar rating. The secondary breakdown is evident in the Si power MOSFET at drain voltages as low as 10 VDS for 1 ms pulses.
Figure 2: Comparison between a BSZ070N08LS5 MOSFET and an EPC2045 eGaN FET safe operating area
Short Circuit Testing
Short-circuit robustness refers to the ability of a FET to withstand unintentional fault conditions that may occur in a power converter while in the ON (conducting) state. In such an event, the part will experience the full bus voltage combined with a current that is limited only by the inherent saturation current of the transistor itself and the circuit parasitic resistance. If the short-circuit state is not quenched by protection circuitry, the extreme power dissipation will ultimately lead to thermal failure of the FET.
The goal of short-circuit testing is to quantify the withstand time the part can survive under these conditions. Typical protection circuits can detect and react to over-current conditions in 2-3 μs. It is therefore desirable for eGaN FETs to withstand unclamped short-circuit conditions for about 5 µs or longer.
Two representative eGaN FETs were tested: EPC2203 (80 V), a 4th generation automotive grade (AEC) device, and EPC2051 (100V), a 5th generation commercial-grade device.
To gather statistics on the withstand time, cohorts of eight parts were tested to failure. Table 2 summarizes the results. EPC2203 was tested at both 5 V (recommended gate drive) and 6 V (VGS(max)), with mean withstand time of 20 μs and 13 μs respectively. Note that the part survives less time at 6 V because of the higher saturation current. EPC2051 exhibited a slightly lower time-to-fail (9.3 μs) compared with the EPC2203 at 6 V. This is expected because of more aggressive scaling and current density of this device. However, in all cases, the withstand time is comfortably long enough for most short-circuit protection circuits to respond and prevent device failure. Furthermore, the withstand time showed small part-to-part variability.
The lower rows in Table 2 provide pulse power and energy relative to die size. To gain insight into the relationship between these quantities and the time to failure, time-dependent heat transfer was calculated to determine the rise in junction temperature, ΔTJ, during the shortcircuit pulse. The results are shown in figure 3.
Table 2: Short-circuit withstand time statistics for EPC2203 and EPC2051. Average pulse power and energy correspond to a typical part within the population.
Figure 3: Calculated junction temperature rise vs. time during the short-circuit pulses for EPC2051 and EPC2203 at 5 V and 6 V VGS. Measured failure times are indicated by red markers.
The intense power density during the pulse leads to rapid heating in the GaN layer and nearby silicon substrate. or EPC2203, both the 5 V and 6 V conditions fail at the same junction temperature rise of 850 °C. The same is true for EPC2051, where both conditions fail at the same ΔTJ of 1050 °C.
Further analysis is required to determine the exact mechanism of failure. Nonetheless, the experimental results presented in this study demonstrate the outstanding capability of eGaN FETs under extreme voltage and current stress.
About the Author
Alex Lidow is CEO and co-founder of Efficient Power Conversion (EPC), former CEO of International Rectifier and is the co-inventor of the HEXFET power MOSFET, a power transistor. He has authored numerous peer-reviewed publications on related subjects, and received the 2015 SEMI Award for North America for the commercialization of more efficient power devices. Lidow was one of the lead representatives of the Semiconductor Industry Association (SIA) for the trade negotiations that resulted in the U.S. – Japan Trade Accord of 1986 and testified to Congress on multiple occasions on behalf of the industry.
- ZVEI Robustness Validation Working Group, Eds., Handbook for Robustness Validation of Semiconductor Devices in Automotive Applications, Third edition: May 2015, Published by ZVEI – Zentralverband Elektrotechnik – und Elektronikindustrie e.V. Available at https://www.zvei.org/fileadmin/user_upload/ Presse_und_Medien/Publikationen/2015/mai/Handbook_for_Robustness_Validation_of_Semiconductor_Devices_in_Automotive_Applications__3rd_edition_/Robustness-Validation-Semiconductor-2015.pdf
- G. Breglio, N. Rinaldi, P. Spirito, “Thermal Mapping and 3D Numerical Simulation of New Cellular Power MOS Affected by Thermal Instability,” Microelectronics Journal, Vol. 31, Issues 9-10, October 2000, pp 741-746
This article originally appeared in the Bodo’s Power Systems magazine.