Technical Article

Selection and Proper Operation of Switching Power Transistors: Part 2

June 23, 2020 by Artur Seibt

With 3 materials and about 8 types of transistors to select from — although not all combinations are available — the choice of the optimum switching transistor is difficult.

In the first article of this series, we discussed the main requirements for power transistors, Si power bipolars, the structure and breakdown of standard Si MOSFET power transistors, and superjunction transistors. 

In this article, we will further discuss the operation of Si MOSFETS in the realm of drive circuits and Si IGBTs. 


5. Drive Circuits for the Proper Operation of Si MOSFETs.

A general remark regarding manufacturers' Application Notes and circuit diagrams: with a few exceptions those are unfit for any series production.

Basically, the drive circuit has to charge and discharge the gate input capacitance, but this is not constant.

When switching from OFF to ON and vice versa the transistor will cross its linear region. Due to the very high transconductance of MOSFETs and JFETs, the capacitance between drain and gate will be multiplied by a high factor. The driver will hence, while crossing the linear region, be severely loaded, this causes the gate voltage to remain on a plateau. Switching will thus be slowed down considerably unless the driver can deliver several amps. Such powerful output stages demand large, expensive chips, especially in CMOS.

Any comparisons of switching speed are meaningless unless the driver is also considered. A resistor in series with the gate is normally required, which determines the speed of turn-ON. It has to be paralleled by a fast diode, a 1 N 4150 (not 4148) is good enough for most medium-sized MOSFETs. The need for this diode is two-fold: it prevents the build-up of too high a voltage across the resistor during turn-OFF, and it speeds up turn-OFF. A driver powerful enough to deliver several amps and a low-value gate resistor minimizes the switching times.

As mentioned short switching times are not only an advantage: they reduce switching losses, but they generate stronger EMI, and the isolation materials in transformers, etc. are subjected to higher dielectric stress. This will not always cause immediate failure, but all isolation materials have a limited life which is dependent upon the operating temperature and the dielectric stress which is given by the operating frequency and the dv/dt. At 100 kHz standard polyester foil takes only 1/10th of the voltage it takes at 50 Hz. This seldomly mentioned when fast switching is praised. See e.g. the life curves for triple-insulated wires.


5.1 Conventional Drivers

The ideal output stage is a low impedance CMOS driver which also clamps the gate at ground and Vcc. As the other circuitry of a driver is mostly bipolar, this requires a BICMOS chip. Therefore most drivers are low-cost bipolar and feature a quasi-complementary NPN output stage with the disadvantage that this can neither pull to ground nor to Vcc, at best down to + 1 V and up to Vcc - 1 V. Si power MOSFETs have a minimum threshold of typically 2 V, some as low as 1 V, so a resistor from gate to ground is mandatory. At turn-ON the upper level is less critical as long it is > 10 V. More than 12 V is unnecessary and only injects excess gate charge which has be removed at turn-OFF.

The leakage current can easily turn the MOSFET on if the impedance to ground resp. source is too high, the maximum leakage current at the highest operating Tj is to be considered. In practice, this resistor should be < 100 K, rather closer to 10 K. Another often overlooked reason: all driver ic's need a minimum Vcc before they operate, below this minimum voltage, is reached, the output to the gate remains high impedance, hence the gate is open-circuit! Disregarding leakage can lead to parasitic turn-on which causes increased losses, but even destruction due to thermal runaway.

If a driver's output stage is too weak a complementary emitter follower can help, a BC 330-40/BC 327-40 is often sufficient.


5.2 The Miller Effect and the Cascode

Both originate from analog high-frequency amplifier circuitry and are known for decades; pulse circuits are just overdriven amplifiers.

Figure 5.1 shows an amplifier of any shape with the gain v and the capacitance CAE between output A and input E. It does not matter whether the amplifier consists of only one transistor or whether there is any number of stages. Also, it does not matter whether it is inverting or not. In any case, the capacitance between output and input sees the difference voltage vIn - vout. This has the same effect as if there was an effective input capacitance Cequ., the "Miller capacitance". Note that this effect is only present when the amplifier is energized; it can then be measured with a capacitance meter. The amplifier must be in its linear range, the effect disappears when the amplifier is over-driven because the gain becomes zero.

Cequiv = C output to input (1 - v).


Figure 5.1: How the Miller effect comes about.
Figure 5.1: How the Miller effect comes about.


The gain v has to be entered with sign.

Note that Cequiv can be higher or lower than the actual C output to input depending on the sign of v! An important practical case is the emitter or source follower with the ideal v = + 1; here Cequiv = 0, both ends of C output to input see the same signal so there is no signal current, the value of C can be any. Another way of expressing is to say that both ends of this capacitance are bootstrapped

Any pulse circuit suffers from the Miller effect because the switching device must traverse its linear region from on to off and vice versa. Mosfets feature a very high transconductance, hence the Miller effect will be pronounced. In the very moment when the transistor enters its linear range, the driver will be loaded with considerably higher capacitance, so the input waveform will exhibit a plateau until the transistor leaves its linear range. For faster switching, high drive currents are necessary which require expensive drivers. In wideband amplifier circuits, the Miller effect can be compensated, this is not possible in pulse circuits. All that is possible is to minimize the external output to input capacitance, due to the tiny transistor resp. ic cases an effective shielding between input and output is hardly possible, a problem which the cascode solves. Switching times comparisons between different transistors are meaningless unless the drive circuits are also considered! Note that is is not possible to feed excessive input currents into a switching transistor because these currents must be sunk resp. generated by the transistor's output.

The cascode, known from high-frequency tube amplifiers, is the ideal switch. The name is a combination of "pentode" and "cascade". It consists of two amplifying devices in series connection as shown in Figure 5.2. There is a great number of cascode circuits, any combination of tubes, bipolar, MOSFETs and JFETs is feasible. including so-called folded cascodes; these consist of transistors of opposite polarity such that input and output can be on arbitrary potentials, also both transistors can operate with different currents. Inside amplifier ic's cascodes are standard.


Figure. 5.2: One of a great many executions of a cascode, here a favourable combnation of a standard n-channel lv mosfet and a jfet, in particular a GaN or SiC jfet. This combination does not require an auxiliary gate voltage. The intrinsic diode of the mosfet is used in bridge circuits where the current must also flow in reverse direction. A jfet passes current in both directions. Most GaN and SiC jfets on the market appear as cascodes.
Figure. 5.2: One of a great many executions of a cascode, here a favorable combination of a standard n-channel lv MOSFET and a JFET, in particular, a GaN or SiC JFET. This combination does not require an auxiliary gate voltage. The intrinsic diode of the MOSFET is used in bridge circuits where the current must also flow in the reverse direction. A JFET passes current in both directions. Most GaN and SiC JFETs on the market appear as cascodes.


The standard cascode is a combination of an lv n-channel MOSFET with the source at the ground and a second one with the gate at (ac) ground. The first one feeds into the source of the second one; it is hence the combination of a grounded-source and a grounded-gate stage.

Ideally, a transistor has infinite input and output impedances, i.e. its drain output is a current generator Ideally a transistor has infinite transconductance, this means that its input impedance at the source is zero, i.e. the source input is a virtual ac ground resp. a current sink. The ac current coming out of the lower transistor's drain enters the source and comes out of the upper one's drain. This has a series of consequences:

1. Except for the cascode type shown in Figure 5.2 cascodes require an auxiliary gate voltage supply for the upper transistor, typically + 12 V. If the lower transistor turns on, it automatically applies the 12 V between gate and source of the upper transistor. Note that a JFET is fully on with zero gate voltage. If the input = gate of the lower one is driven, the source of the upper one (JFET) is pulled to zero, so the voltage between gate and source becomes zero. The capacitance gate-to.source of the upper is discharged by the extremely low (milliohms) Rdson of the lower one. If the lower one is turned off, the ac source current of the upper one quickly charges the capacitance at the node lower drain-upper source until the voltage at this node reaches the pinch-off voltage of the upper one, turning it OFF. The voltage swing is only between zero and Vpinch-OFF, i.e. < 20 V, so a small lv MOSFET is sufficient. In practice, a Zener is required at this node limiting the voltage during switching. The additional cost for turning a single Coolmos into a cascode is minimal.

2. Due to the zero impedance of the source (as an input) there is no ac voltage at the lower's drain, hence there is no Miller effect. The input capacitance of the cascode is the lowest possible and consists only of the sum of gate-to-drain and gate-to-source capacitances. The cascode is the easiest- to- drive switch. This one reason why it so fast.

3. The connection between the lower's drain and the upper's source is uncritical because there is no ac voltage, the signal is a pure current, the capacitance to ground sees no ac voltage and does not affect the switching. Both transistors can, therefore, be set apart, so the critical capacitance output-to.input can be minimized in order to avoid "Miller effect all around". This would be detrimental because the gain of a cascode is the highest achievable in one stage, it is simply the product of the transconductance of the lower transistor times the load impedance of the cascode. The upper transistor sees the output impedance of the lower one in its source; this is infinite because it is a lv mosfet. So even if the upper transistor is a JFET with a fairly low output impedance the output impedance at its drain = cascode output is practically infinite. Therefore very high load impedances are possible (in amplifiers) and gains of several thousand. However, the inductance of the interconnection is critical. The board layout of a cascode is a challenge. This is a GHz circuit resp. an ns switch. Even offline voltages like 360 V can be switched in < 5 ns.

4. It is vital to realize that the (ac) grounded-gate upper stage does not amplify, but it just passes the ac drain current of the lower transistor along to its drain = output. The upper transistor can be almost any: a high fT bipolar, a standard MOSFET, a Coolmos, a-Si, GaN, SiC JFET, a GaN or SiC enhancement MOSFET, it does not matter! This is very important to understand because GaN and SiC manufacturers that offer cascodes try to convince customers that GaN resp. SiC causes fast switching. In fact, if a Si Coolmos is used in place of the GaN or SiC the switching speed is identical because it is solely the merit of the lower standard Si MOSFET. Why none of the Coolmos (Superjunction) manufacturers put cascodes on the market is hard to understand. The GaN resp. SiC cascodes have no advantages whatsoever in switching stages with one exception: bridge circuits where the intrinsic diode of the lower MOSFET passes current in the reverse direction. Both GaN and SiC have no avalanche ratings. The lower capacitances of GaN or SiC are hardly noticeable because there are always at least 3 components at a node. In the simple case of a PFC, the contribution of the switch is much lower than that of the choke or the SiC diode.


5.3 Additional Hints

1. The susceptibility of ic's to current fed into their outputs varies widely; if the ic's from one manufacturer will function the same type ic from another one will be destroyed.

2. The ubiquitous cheap polyester insulation on inductive components is not really safe for offline SMPS; above 130 C it will disintegrate. The withstanding voltage decreases sharply with the frequency; at 100 KHz polyester will only take 10 % of the voltage at 50 Hz! Higher temperatures also decrease the withstand-ing voltage and the life of the material. The triple-insulated materials like TexE consist of polyester and nylon layers. If such a transformer burns, contact between primary and secondary becomes possible. Kapton is more expensive, but it withstands 400 C and disintegrates at 800 C, it is also, next Teflon, the best dielectric we have. Hence two layers should be used as insulation between primary and secondary in offline transformers.

3. Due to their avalanche-proof protective components in the drain of Si power MOSFETs are normally not necessary, however, as mentioned, continuous avalanching is not advisable, also because it generates additional losses and EMI. The highest stress is in flyback circuits. For offline SMPS 800 V MOSFETs are not necessary, 650 V Coolmos will do. A damper circuit consisting of a fast high voltage diode such as BYV 26 E and a parallel combination of a resistor and a PP or ceramic HV capacitor should always be provided. Additional RC's in parallel with the primary and secondary windings may be necessary; the capacitors must be NPO, the resistors non-inductive. In order to keep losses low, the capacitor should be as small as possible, typically < 100 p.

4. Use only 100:1 probes with appr. 2 p and watch the ground return: best is the use of a Tektronix probe receptacle.

5. The insulation material between the transistor and the cooling surface is critical and often underestimated. The high dv/dt generates substantial dielectric currents through the insulation which not only creates losses therein but generates strong EMI. Ceramic materials are best but expensive and difficult to install. The best compromise is 0.4 mm silicon rubber filled with ceramic powder (e.g. Kerafol,86400.) Thinner material is likely to be damaged by the uneven surface and sharp edges of the transistor. Note that the Rth between the chip and the cooling surface is increased, but is seldomly specified. It is best to measure it by mounting a resistor in the same case as the transistor, e.g. TO-220, with the same material.

6. Even if there is no potential difference between transistor body and cooling surface do not expect both to be flat; at best there will be a line or point contact and thus poor heat transfer. Grease is obsolete and highly undesirable in production environments. The industry has developed interface materials that are dry at room temperature. When the transistor heats up the first time grease will ooze out and fills the gaps for optimum heat transfer.

7. If especially low EMI is asked for, e.g. in medical equipment, and if thick ceramic insulators are not desired, it is possible to use stacked insulation, i.e. first an insulator, then a copper foil and then a second insulator. The copper foil is connected to the same ground as the switching transistor. Beware of Kapton here, because its heat transfer is very poor!

8. Transistor mounting with screws or even rivets is out, the only acceptable method is the use of spring clamps which press upon the plastic body. This is the only way to uphold enough pressure over time.

9. Temperature measurements on the live drain of an active switching transistor will disturb most instruments, the high capacity of the probe can also interfere with the operation. One measures hence directly after turn-off.

10. The power dissipation can only be approximately calculated, turn-ON and turn-off are complicated. The best method: One measures the case temperature directly after switching off. Then one mounts a TO-220 power resistor in place of the transistor with the identical insulation. With a power supply, one heats the resistor to the same temperature the transistor had; the power required is identical to the transistor's dissipation.

12. The inverse diode is in fact the collector-base diode of the parasitic NPN and quite slow; there are MOSFETs with faster ones. One has to be careful when turning these diodes on during switching, this may cause destruction.


6. Si IGBTs.

One of the most commercially successful inventions was the IGBT =insulated gate bipolar transistor. It is ubiquitous.

The IGBT offered a fundamental solution to the problem of the loss increase with the square of the current with MOSFETs. It is a bipolar transistor driven by a MOSFET; as such it can simply mobilize more charge carriers, i.e. electrons as well as holes. The voltage across it only increases very little with the current. This feature and the lowcost explain the enormous economic importance of the IGBT: almost all drive electronics in the transportation business rely on IGBTs.

Hvbipolars suffer from very low current gain, this problem is remedied by the MOSFET input. However, during turn-off, the bipolar is left with an open base, a horror to every experienced design engineer. The turn-OFF is slow, so the IGBT suffers from high losses during turn-off. This is why it is confined to low-frequency operation with offensive audible noise from traction vehicles. Meanwhile, there are approximately 7 generations of IGBT's on the market which also allow supersonic operation. Only lately SiC transistors started to replace IGBTs due to their much higher operating frequency, low Rdson's, and also higher operating TJs. Their disadvantage is the higher cost.


Figure 6.1: Differences between the two mosfets and an IGBT. Note the tail current.
Figure 6.1: Differences between the two MOSFETs and an IGBT. Note the tail current.


Figure 6.1 shows the differences between the MOSFETs and the IGBT. The backside p layer (pnp collector, with IGBTs called "emitter") injects additional charge carriers. These charge carriers are in balance with the electrons in the channel, hence a much greater concentration of charge carriers is created as that caused by the doping, hence the conductivity of the drift zone is increased. But during turn-OFF, these additional charge carriers have to be removed from the drift zone which causes the long "tail" of the current. Operating frequencies remained mostly in the kHz range.

The saturation voltage Vsat can not be appreciably decreased and also the losses while the Rdson of SiC MOSFETs reaches milliohm regions. A major advantage of the IGBT is its low cost because it remains a bipolar transistor. Note that the main difference to a standard MOSFET is the additional bottom p layer.

There are two families of IGBT's: PT = punch-through and NPT = non-punch-through. The difference lies in the form of the electric field. In the NPT the field does not reach into the backside emitter, the wafers are inexpensive with one doping.

SiC MOSFETs will always remain more expensive, but their use allows savings otherwise, e.g. in the passive components. In the long run, they will replace IGBTs


Come back next month for the third installment of this series. 


About the Author

Dr. Artur Seibt is a professional electronics design lab consultant with a specialization in SMPS with 40 years of experience in SiC, GaN, D amplifiers. He is the inventor of current-mode control (U.S. Patent) and he is also an expert in EMI design.