Novel Technique to Reduce Substrate Tilt amp Improve Bondline Control between AlN Substrate and AlSiC Baseplate in IGBT Modules
This article features a novel technique to redue substrate tilt and improve bondline control between AIN substrate and AlSiC Baseplate in IGBT Modules./></body></html>
Large area solder joints in multi-chip power semiconductor packages experience fatigue caused by the periodic straining of the interconnection layers during thermal excursions as the device is operational. These stresses lead to delamination and cracks within the solder layer after many thermal cycles which increase the junction-to-case thermal resistance and ultimately lead to early device failure
Cracking and solder layer delamination occur earlier in inhomogeneous solder joints due to stress concentration at thinner areas of the joint, Figure 1 shows how crack length within the solder joint increases greatly with solder layers thinner than 200µm. This figure illustrates how tilted samples, where part of the joint is <200 µm, are more susceptible to cracking and delamination.
Figure 1: Correlation between solder joint thickness and induced crack length after thermal cycling 
Figure 1.1: Substrate tilt example (top) and solution using wire bonds to achieve bondline uniformity (bottom) 
The advent of spacer technology allows control of the solder joint thickness for a given solder volume by reducing substrate tilt to achieve a homogenous solder layer, as Figure 1.1 demonstrates. This is most commonly done in power semiconductor modules by stitch bonding aluminum wire of the desired diameter to an AlSiC baseplate: for copper baseplate modules, copper ‘bumps’ can be stamped in the component (Figure 1.2).
Figure 1.2: Traditional bondline control methods, aluminium wirebonds on AlSiC baseplate (left) and stamped ‘bump’ in copper baseplate (right)
The use of spacers in large area solder joints increases the joint lifetime by allowing for homogenous delamination. This occurs at a much slower rate than inhomogeneous delamination caused by substrate tilt [1-2]. This technology is well documented and employed today in power module assembly, but this technique results in a high cost of ownership due to extra process steps and capital equipment costs.
InFORMS® are reinforced solder preforms with an embedded mesh, offer an alternative solution to achieve a homogenous solder layer. When the solder melts during reflow, the reinforced matrix remains intact and serves to maintain uniform bondline thickness. InFORMS® offer a drop-in solution to standard preforms and eliminates the additional process steps associated with the traditional aluminium stitch bond method. This study evaluates the lifetime of InFORMS® against the traditional aluminium stitch bond method.
The same soldering profile and identical process steps were used to assemble modules with InFORMS® as well as modules with the traditional wirebond method, for achieving a homogenous solder layer. These samples were also compared to reference modules with no bondline control; four of each variant were tested. The samples were then temperature cycled chamber to chamber with a ΔT of 200 K; cracking and delamination of the solder layer were monitored by scanning acoustic microscopy every 200 cycles. Module assembly consisted of soldering ceramic AlN substrates (with Cu metalisation) to 140x70 mm AlSiC baseplates using 200 µm SnSb5 solder preforms. The samples with the InFORMS® consisted of a 200 µm mesh with a 225 µm net solder thickness. The samples with aluminium stitch bonds used 180 µm diameter wire. These were compared to 200 µm thick preforms with no bondline control. 200 µm is the targeted bondline thickness as this offers the lowest thermal resistance without suffering from increased strain.
Following the assembly of the samples, one of each sample type underwent a laser surface profiling scan to determine the substrate tilt prior to thermal cycling tests. This was determined as the mean height variation across the top of the substrate at four points; maximum deflection was also measured. The InFORMS® sample shows the least coplanarity deviation (smallest ΔZ) at 52.5 µm and a maximum deflection of ~60 µm (Figure 3), followed by the wirebonded sample at 56.5µm with a maximum deflection at ~70 µm, and finally the sample without bondline control at 67.5 µm and a maximum deflection of ~90 µm. It is noticed that on all samples the substrates are tilted inward toward the baseplate, owing to the concave shape of the baseplate.
Figure 2: Assembly images showing sample soldered with InFORMS® (top) and sample with wirebond spacer (bottom).
Figure 3: Each sample type underwent a laser surface profiling scan to determine the substrate tilt prior to thermal cycling tests.
Samples were thermal cycled using a Vötsch VT 7012 S3 chamber to chamber thermal cycler. The samples were cycled from -50°C to 150°C under the following conditions.
tdwell = 1 hour Ts(max) = 150°C
ttransition = 30 seconds Ts(min) = -50°C ΔT = 200K
Figure 4 shows the SAM images at zero, 600 800 cycles of the baseplate/solder interface for all three techniques. Delamination of the solder layer is witnessed as bright reflections emanating from the edges of the solder layer. No delamination was witnessed at 200 and 400 cycles for all bondline variants. At 600 thermal cycles for the samples with no bondline control, delamination was observed. Cracking was witnessed in the secondary SAM gate, reflecting the substrate/solder layer by showing bright reflections indicating cracking. No delamination or solder cracking was seen for the InFORMS® samples or wirebonded samples at 600 cycles.
Figure 4: SAM results at zero, 600, and 800 cycles
At 800 cycles, solder cracking was observed with the samples made with Al wirebonds (Figure 5). These appear at the same location where the solder layer is at its thinnest due to the concave nature of the baseplate. The InFORMS® samples showed no signs of cracking or delamination at 800 cycles (Figure 5).
Figure 5: 800 cycles; Secondary SAM gate highlighting cracks in the solder layer for samples with Al wirebonds. No signs of cracking/delamination for the InFORMS® samples.
At 1000 cycles, the InFORMS® samples still showed no signs of cracking or delamination (Figure 6). Some solder cracking/delamination was observed with the samples made with Al wirebonds. Severe cracking was observed on the samples with no bondline control.
Summary and Conclusion
A novel technique to prevent substrate tilt and maintain a homogenous 200µm solder layer using InFORMS® with an embedded metal mesh was evaluated and compared to the traditional aluminium stitch bond technique for AlSiC baseplate modules. These were also compared to samples with no bondline control.
Figure 6: 1000 cycles; InFORMS® No delamination/solder cracking observed in InFORMS®; Some delamination/solder cracking observed in Al wirebond samples; Sever cracking observed in samples with no bondline control.
Surface profile scan to determine substrate tilt showed that InFORMS® samples had the lowest co-planarity deviation of 52.5 µm. The samples were subject to temperature cycling (-50/+150C) to observe solder layer delamination/cracking of the solder joint. At 600 thermal cycles, the samples with no bondline control first showed cracking at the tilted side with a difference of ~90 µm – the lowest side of which emanated cracking and delamination. At 800 thermal cycles, the samples with Al wirebonds showed signs of cracking with some, but not all samples; again with cracks appearing at the thinner end of the solder joint, i.e., the centre of the baseplate. No cracks or solder delamination were seen for the InFORMS® samples at 600 or 800 thermal cycles. Even at 1000 thermal cycles, the InFORMS® samples did not show solder cracking/delamination.
While the effect of bondline control has already been studied and shown to improve joint lifetime in power modules, using InFORMS® presents a more reliable method as opposed to the aluminum stitch bonding method. The reinforced matrix in the InFORMS® supressed solder fatigue by resisting creep and showed improved reliability compared to the traditional wirebond method. InFORMS® also offer a drop-in replacement to achieving bondline homogeneity, without additional process steps of wirebonding and associated capital equipment costs, thereby providing the lowest cost of ownership.
About the Authors
James Booth works as the Senior Engineering Technician at Dynex Semiconductor Ltd., where he is specialized in research and presentation. He earned his Higher National Certificate in Electrical and Electronics Engineering at Lincoln College located in Lincoln, England. He then acquired his Bachelor of Engineering degree in Materials Engineering at Sheffield Hallam University, England.
Karthik Vijay is based in the UK and is responsible for technology programs and technical support for our customers in Europe. His expertise is focused on engineered solders (power electronics), solder paste, thermal interface materials, and semiconductor-grade electronics materials. Karthik joined Indium Corporation in 2003 and has over 15 years of experience in electronics assembly. He has a master’s degree in Industrial Engineering with a specialization in Electronics Packaging & Manufacturing from the State University of New York, Binghamton. He is an SMTA-certified engineer and earned his Six Sigma Green-Belt certification from Dartmouth College’s Thayer School of Engineering. He is active in several industry organizations, including IMAPS, SMTA, and has presented at several industry forums and conferences nationally and internationally.
- K. Hayashi & G. Izuta, “Improvement of Fatigue Life of Solder Joints by Thickness Control of Solder with Wire Bump Technique,” ECTC 2002
- K. Guth & P. Mahnke “Improving the thermal reliability of large area solder joints in IGBT power modules,” Integrated Power Systems (CIPS), 2006
- L. Mills & K. Vijay “InFORMS vs the Trimmed Wirebond Technique to Achieve Uniform Bondline Control Between Substrate and Baseplate,” PCIM Europe 2015 James Booth, Dynex Semiconductor Ltd - [email protected] Karthik Vijay – Indium Corporation - [email protected]
This article originally appeared in the Bodo’s Power Systems magazine.