High CV MLCC DC BIAS Capacitance Loss Explained

MLCC capacitors are dominating today’s capacitor market enabling high grade of electronics miniaturization. The continuous downsizing and use of higher and higher dielectric constant materials for MLCC class II capacitors has however resulted in worsening of some electrical parameters such as capacitance drop at operating conditions.

Thus, in consequence, what can be considered as an enabling technology for consumer and wearable applications may pose some risk if used in critical applications such as automotive, safety, medical or industrial sector, that are also in need for continuous miniaturization. In many cases, capacitance loss data available from MLCC manufacturers are given as “typical” performance leaving responsibility for “guaranteed” operation to the electronic system designer.

 

MLCC Capacitance Ageing with Time

The MLCC class II capacitors are using BaTiO3 ferroelectric materials as a high dielectric constant material to achieve its very high capacitance values in small dimensions. Downside of this material is its strong dependency on operating conditions – namely loss of capacitance – with DC Voltage (DC BIAS), AC Voltage, temperature and ageing with time. In addition, piezo noise may degrade smoothing capabilities of these capacitors at certain condition.

BaTiO3 has a cubic crystal structure above the Curie temperature (approx. 125°C or more), but below the Curie temperature it turn into a different crystal structure (tetragonal) that creates a dipole, respectively domains of dipoles with different dipole orientations that reduces its original polarization and reduces its capacitance values. The dielectric grain size/shape/distribution may impact number of dipoles and domains and the capacitance loss. As this structure changes with time, dielectric constant is reduced and over time, the capacitance continues to decline.

 

Table 1: MLCC typical aging and referee time. source: Kemet

 

Capacitance Ageing effect depends to MLCC dielectric type and it is constant per time decade (so the process slow down exponentially). Typical values see Table 1 above.

Various manufacturers use different time, but the most common reference points are 48 or 1kHz as also shown in table 3. with note that manufacturers are measuring capacitance with one day or twenty-four hours after “last heat” that is also in accordance to MIL specification conditions. (Re)heating to Curie temperature “reset” the structure and returns capacitance value to its initial value.

 

MLCC Class II Capacitance with DC BIAS

Some of the BaTiO3 dipoles are also blocked by DC voltage and it cannot move further with small AC voltage changes resulting in loss of capacitance.

The level of Capacitance loss (number of blocked dipoles) is proportional to the DC field (V/mm), thus capacitor with thinner dielectric and higher volts per dielectric thickness exposure will exhibit higher capacitance loss with DC BIAS. Type and structure of the dielectric (grain size, shape, distribution, impurities) may have also a significant impact to the capacitance loss level.

In consequence, the capacitance loss level may increase with higher CV density (high capacitance in small dimensions) and it may be part number and manufacturer specific. See figure 1. below as an example. The loss at rated voltage can vary from -35% to -65% at rated voltage that may result in significant different performance among manufacturers.

 

Figure 1: Capacitance loss with DC BIAS on 10μF 6.3V MLCC X7R 0805 case by three different vendors; source: EPCI using manufacturers’ datasheets

 

It may be of critical importance to evaluate such characteristics when qualifying alternative MLCC manufacturer.

The drop of capacitance due to DC BIAS is not happening immediately, but some time is needed for slower dipoles to be completely blocked. Thus, we can see some fast-immediate drop of capacitance at time close to zero after DC Voltage plug in, and some additional drop within tenth of minutes to hour(s) to get to final capacitance drop level. See Figure 2.

Once all dipoles are blocked there is no further significant impact of DC voltage in longer timeframe. MLCC manufacturers use to talk about behaviour of the capacitor in decades ... so what happens in first decade, second decade etc. as this is directly link to physical mechanisms and its impact to overall performance.

 

Figure 2: Capacitance drop with time under DC Voltage BIAS; source: Panasonic

 

The Capacitance loss with DC BIAS effect can be reduced by using a physically larger case that reduces V/mm electrical field exposed to the dielectric. See Figure 3 as an example of 0805 vs 0603 case sizes. Another choice, if applicable, is to use a higher-grade dielectric type material such as moving from X5R to X7R or tighter tolerance field e.g. moving from X7R to X7P. See Figure 4 as an example of X5R vs X7R capacitance loss with DC BIAS on 1uF 6.3V 0402 types.

 

Figure 3: Example of 0805 vs 0603 10μF 6.3V X5R capacitance loss with DC BIAS voltage

Figure 4: Example of X5R vs X7R capacitance loss with DC BIAS voltage on 1uF 6.3V 0402

 

MLCC Class II Capacitance with AC Voltage

Ferroelectric materials (BaTiO3) exhibit some hysteresis in polarization as a function of electric field that is causing MLCC capacitance dependency also to AC voltage. The level depends mainly to the dielectric type as shown in Figure 5.

The reference standard capacitor AC volt measure conditions are set to 1Vrms at 1kHz and room temperature. Nevertheless, there are number of MLCC capacitor applications that are operating at significantly lower AC voltage such as 10mV. In this case we can expect capacitance drop of capacitance due to the small AC voltage in range of additional -5 to -15%.

The “AC voltage hysteresis” is also “resettable” by heating of the capacitor to Curie temperature.

 

How to Specify MLCC class II DC BIAS Capacitance loss

This chapter propose definition of MLCC class II capacitance loss for future specification:

Capacitance loss guaranteed not to exceed XX% (for example -70%)1 at 100%2 of rated voltage, measured at reference conditions: after 12hrs3 post last de-ageing and DC BIAS voltage applied at least for 10hrs4 at RT, 1kHz and 1VAC.

Procurement specification proposal to be agreed between customer and supplier on each PN under qualification:

The supplier shall also provide typical Capacitance loss with DC BIAS charts or link to an on-line simulation tool. Such specification would help designers to see some fixed capacitance loss guaranteed working point and evaluate the worst case at the edge operating conditions.

 

Figure 5: Capacitance change with AC voltage by different dielectric types; source: Murata

 

Customer Designer Guidelines:

• If you discover that this capacitor is unsuitable due to the capacitance loss as defined in the specification above, you have the following options:

• You can check if lower Capacitance DC loss / piezo suppression series is available by a manufacturer (need check with purchasing team as this can be more expensive part or single source)

• Use a larger capacitance value so that when the capacitance loss is considered, you still have enough capacitance for the required functionality. Note: higher values may have even worse DC bias characteristics due to even higher CV factor. This also may be an issue of distortion in large-signal AC, and likely will just make the problem worse and may not lead to the problem solving.

• Use a physically larger package size. This would reduce V/mm electrical stress and thus reduces also DC BIAS capacitance loss dependency. So, if you have enough room in your design, moving one step up in case size, for example from 0402 to 0603, 0603 to 0805 or a 1210 will significantly reduce the issue.

• If applicable, you can consider using more stable dielectric type such as moving from X5R to X7R, from X7R to X8R dielectric type or tighter tolerance field such as from X7R to X7P types. (multi-sourcing and price increase options to be checked)

• Use a different capacitor type. Sometimes, you won’t be able to escape the DC bias issue or piezo issues at all. In this case, consider looking at a different capacitor type, such as an aluminum hybrid if you have enough board space or a tantalum polymer capacitor that may provide low profile, high CV and stable option.

 

Notes:

1. The level of defined maximum capacitance loss may be a part number specific, the actual value or some more detail guideline, if possible, to introduce some general rules to be discussed with manufacturers.

2. The cap loss reference DC BIAS is suggested to 100% of rated voltage, but it can be changed upon discussion with manufacturers. If suppliers are pushed to “legally” guarantee the worst capacitance drop, they will have to 100% measure and screen their production. The standard way of mass production 100% electrical capacitance measurement today is by CLR measure bridge with small BIAS 1-2V. There are two ways to measure capacitance at higher BIAS voltage:

• use of external BIAS source with CLR measurement bridge or
• indirect capacitance measurement – from I=C*dV/dt, for example to use IR measurement with 100%Vr charging for capacitance calculation and correlate it to the CAP loss characteristics.

3. the best fit method with low introduction cost, consistent correlation and quick implementation to be discussion with capacitor manufacturers, as one of the targets for panel discussion.

4. 12 or 24hrs measurement after last heat/deaging is a standard time used also in MIL standards to define state of the dielectric after the last “reset”.

5. 10hours of DC applied as reference selected in respect to decades behaviour references that is used by MLCC manufacturers ... what is happening in first, second, third decade ...etc. 1hour may not be sufficient in some cases to see all slow polarization to happen and need to add some safety, thus 10hours (or more) is set as the reference point.

The next PCNS 2019 Passive Components Networking Symposium September 10-13th, 2019 in Bucharest, Romania will introduce MLCC Class II DC BIAS & Ageing Capacitance Loss as the Hot Panel Discussion Topic to initiate discussion between manufacturers and users on this topic.

 

About the Author

Tomas Zednicek holds a Ph.D. in Tantalum Capacitors and a Master's Degree in Electrotechnology both at the Technical University Brno. He is the President and Founder of the European Passive Components Institute since July 2015.

 

This article originally appeared in the Bodo’s Power Systems magazine.