Class 2 MLCC Dielectrics and the Case of the Missing CapacitanceJuly 03, 2018 by Steve Hopwood
This article discusses two different characteristics of the Multilayer Ceramic Chip Capacitors.
Most designers selecting an MLCC for their application will be familiar with the dielectrics being described as class 1 or 2, but may not be totally familiar with what this actually means, or what impact it can have. MLCC’s are often advertised with their temperature coefficient of ceramic (TCC) figure, but their voltage coefficient (VCC) is often overlooked or ignored. In practice, even the TCC figure can be misleading and the VCC figure can have a much larger impact on the actual effective capacitance of the part. In this article, we consider what the two different characteristics actually mean, and what impact they can have.
Class 1 and Class 2 Ceramic Dielectrics
Ceramic dielectrics are split into 2 classes depending on their basic characteristics: class 1 and class 2. These characteristics are reflected in the 3-figure dielectric codes issued by the EIA – examples below.
Table 1. Class 1 dielectrics are the most stable but have the lowest K (dielectric constant) value, so cannot achieve the highest capacitance values.
- C0G (0±30ppm/ºC) is the most common followed by U2J (-750±120ppm/ºC)
- C0G is the same as NP0 (negative-positive zero)
- P90 (positive 90) is also sometimes seen
Table 2. Class 2 dielectrics have much higher K (40 to 50 times that of C0G) meaning much higher capacitance is obtainable but is less stable with a greater variation with changing temperature or applied voltage.
- X7R (-55ºC / +125ºC / ±15%) and X8R (-55ºC / +150ºC / ±15%) are the most common
- X7S (-55ºC / +125ºC / ±22%) and X7T (-55ºC / +125ºC / +22%/-56%) are also sometimes encountered
These codes enable us to predict the maximum change of capacitance over the temperature range, but here there is the first possibility of confusion – what do the figures actually mean?
Class 2 are the easiest to deal with – taking an X7R capacitor as an example, the capacitance change due to temperature will lie within the boundary of +/-15% from -55ºC to 125ºC. Note, this is not +/-15% of the nominal capacitance value, but +/-15% change from the ambient temperature starting capacitance value. For example, we have an X7R capacitor with a +/-10% stated tolerance. The capacitance value at ambient could be -10%. Over the operating temperature range, the capacitance value could change -15% from this value, so down to a potential 76.5% of the nominal capacitance value.
Class 1 are harder to calculate. Take a C0G MLCC with a change of 30ppm/ºC. Assuming the nominal value is measured at 25ºC, then we have a potential worst-case temperature change of 100ºC, so the capacitance can change by (30x100 =) 3000ppm/ºC or a maximum of 0.3%. This may seem very small, but these capacitors can sometimes be purchased with a minimal tolerance of +/-0.1%, so it should be considered.
Variations Between Components
Note that dielectric classifications X7R / C0G etc are not types of dielectric material themselves. Each manufacturer may use several types of dielectrics across their range, each with its own TC curve, so there is likely to be natural variation within the components.
These figures only give the figures for change with temperature. Class 1 devices suffer minimal change with voltage—so low they’re assumed to have no change. However, the change with voltage can be shocking for class 2 devices as much as 85% to 90% drop with full-rated voltage applied.
Why is this a shock? It’s a figure that tends to be ignored, but why? Has it always been like this?
Figure 1. Typical VC curve for an X7R (Type 2) MLCC
Consider the factors that affect the VCC alongside those that define the actual capacitance of an MLCC. VCC is controlled by the characteristics of the dielectric material and the electrical stress applied to that material expressed in Volts per micron.
Design capacitance is calculated using:
Where: C = total capacitance
n = number of active electrode pairs (individual single-layer capacitors)
K = dielectric constant of the ceramic material
d = dielectric thickness between layers
Figure 2. Chip Capacitance Graphic
New dielectrics have been developed over the years, but these have concentrated on environmental issues (e.g. lead-free dielectrics) or improved reliability. There have been no real improvements in K or VCC performance of the materials. Dielectric constant ‘K’ has remained relatively the same, but dielectric thickness ‘d’ has got significantly less as improvements in manufacturing have resulted in reliable thin layers.
When MLCC’s were first developed the manufacturing technology of the time couldn’t achieve very thin dielectric thickness and consistent reliability, so the VCC performance wasn’t as bad – thick layers resulted in Low V/micron stress levels. As manufacturing improvements over the years have enabled thinner and thinner layers to be realized, manufacturers have either reduced the electrode count (reduced cost) or used the improvement to offer higher capacitance in smaller case sizes for the same voltage rating. These manufacturing improvements have yielded the high-reliability components that we take for granted today, but have also been used by the supplier to maximize the capacitance per unit volume.
The extreme headline figures each manufacturer strives for mean much higher voltage stress on the part—more volts per micron on the dielectric, meaning the actual capacitance/voltage curve drops off much more significantly under the applied voltage.
Headline capacitance values are not always what you’ll have under full operating voltage. Take time to understand how your components will perform and discuss what the actual performance is with the supplier.
About the Author
Stephen "Steve" Hopwood has 30yrs experience in MLCC industry, specializing in capacitor applications and EMI filters using MLCC capacitors. He was previously a design and process engineer in MLCC and EMI filter manufacturing, before moving to applications engineering providing technical support to customers. Currently, He works as an Array Engineering Manager / Senior Applications Engineer at Knowles Precision Devices since May 2019.
This article originally appeared in the Bodo’s Power Systems magazine.