Helping Power Solutions Keep Up With Moore’s Law

When evaluating any system (or collection of systems) in terms of the power solution(s) and/or other analyses related to power consumption, energy efficiency, or overall energy/carbon footprint, it helps to separate the sources from the loads.

 

Separating the Source & Load

In the simplest form, that is separating the power supplies/solutions from the end loads consuming the power these sources provide. Think of the sources and loads as independent black boxes that “talk” to each other. Figure 1 shows an arbitrary breakdown of a system in block diagram form, in this case, a computing or server-like architecture highlighted to show the difference between the typical sources and typical loads in the system.

 

Figure 1. System Block Diagram Separating SOURCES from LOADS, courtesy of PowerRox [1]. Image used courtesy of Bodo’s Power Systems [PDF]

 

This distinction of separating the sources from loads is particularly important when trying to understand the pace of technology in a complicated system that contains numerous components (perhaps each complicated system in its own right) impacted by an endless number of engineering, manufacturing, supply chain, and global economic variables. It is no coincidence the trends of exponential improvement (whether it be a metric characterizing transistor count, feature size, power density, energy efficiency, etc.) tend to be far more associated with the load side than the source-side source side of things. The source-side components tend to be dominated by magnetics, power transistors, and energy storage. These kinds of components tend to double their key figures of merit (FOM) closer to each decade than each year, like low-voltage semiconductors.

 

What Does Moore’s Law Have to Do With Power Solutions?

The consideration of the pace of development of roadmaps for electronics and electrical equipment will commonly converge around Moore’s Law [2], which is more of an economic trend of transistor scaling as opposed to any kind of technical scaling rule (see Dennard Scaling [3]) or physical law in the traditional sense. So even if not technically tracking any of this stuff, there seems to be a general perception in the electronics industry that everything (e.g., all components, supply chains, and engineering efforts) somehow adhere to this pace of doubling performance every 18-24 months. Of course, even the semantical definition of “performance” can be the target of much debate, so that will be left to the wayside for the purpose of this discussion.

Aside from Moore’s Law’s impact on transistor size/count in an integrated circuit (IC), there is another trend driving major system power budget reductions. Moore’s Law keeps logic shrinking at an exponential pace, and microelectromechanical systems (MEMS [4]) shrink and integrate sensors to the point of being nearly invisible to the naked eye. It should be clearly distinguished, though, that Moore’s Law tends to drive a major increase in load power (i.e., per transistor, power goes down, but packing in more of them makes the power density or dissipated power in a given footprint to constantly go up), where MEMS tend to drive a major decrease in load power because applications will not tend to necessitate an exponential increase in the number of sensors even with an exponential decrease in individual sensor power. On the other hand, MEMS is driving the integration of multiple sensors (and sometimes co-packaging of processing and/or communications as well) though this will be discussed in more detail in the next section.

With a reduction in transistor feature size comes a reduction in threshold voltage, which effectively means ICs can operate with ever-decreasing bias voltage rails. This is why microprocessors went from requiring ~2.5/3.3 V rails to ~1.2/1.5 V rails, and now even <<1.0 V power rails. As mentioned, power density still tends to increase by packing in more of these lower-voltage transistors, which translates into a constant trend of driving up the input currents demanded by these dense loads. The densely packed loads also put a bigger strain on power supplies by increasing the transient demand in terms of faster voltage (~100 V/ns) and current (~1,000 A/µs) transitions.

 

How Do Power Solutions Keep Up With the Pace of Moore’s Law?

As highlighted in many resources regarding the design and optimization of power solutions, the most common FOMs for a system are its size, weight, and power (also known as SWaP factors) characteristics. When combined with a cost metric, this can also be referred to as SWaP-C factors [5]. It is obvious how shrinking loads drive regular SWaP improvement, but less so on the source side.

In the more pragmatic sense, it seems the conversation should be around how system components, particularly power solutions in the context of this blog, are enabling systems to take advantage of the advances brought on by Moore’s-Law-like, generational improvement in compute transistor density and integration of MEMS devices. The power solutions are not required to shrink with the low-voltage transistors or even meet their power densities at a 1:1 ratio to enable systems to utilize the evolutionary enhancements of the loads.

The increased transients described above will organically drive the need to bring the power supply closer to the high-transient load. This is not only for efficiency optimization by mitigating thermal dissipation (P=I2R) and voltage drop (V=IR), made more challenging by higher currents, but also for preventing catastrophic voltage overshoot resulting from even little bits of parasitic equivalent series inductance (ESL, 1s – 10s of nH) previous considered negligible in older generations of systems. This highlights a major design challenge for power solutions that work to keep up the pace with Moore’s Law and MEMS by utilizing faster power switches, particularly using wide bandgap (WBG) chemistries, such as gallium nitride (GaN), silicon carbide (SiC), gallium arsenide (GaAs), or aluminum nitride (AlN) [6]. Figure 2 highlights how such little ESL, from the component package alone, can have catastrophic effects on your design. This is even before one has put extreme time and effort into a very clean, tight layout that contains these current flows as best as possible. It should be noted that a lack of research and development in the advancement of high-frequency magnetics materials is currently the ultimate bottleneck in unlocking the full potential of ultra-fast switching speeds WBG power switches are capable of.

\[\Delta V_{overshoot}=L_{parasitic}\times di/dt\]

 

Figure 2. Calculation of Parasitic-inductance-induced Voltage Overshoot by Common Device Packages and Characteristics, courtesy of PowerRox [7]. Image used courtesy of Bodo’s Power Systems [PDF]

 

Integration and advanced packaging techniques are the driving force keeping power solutions on pace with their shrinking load counterparts. Moore’s Law directly facilitates power conversion by allowing the integration of power management and control functionality into more consolidated power management ICs (PMIC), which can integrate power conversion (even integrating power switches), control logic, power conditioning, digital control and/or telemetry reporting, and management of external energy storage and feedback. This integration of power subsystems brings discrete solutions into the IC domain to dramatically reduce board footprint space, along with enhancing control and optimizing the overall efficiency of energy commutation.

Heterogeneous integration of MEMS sensors along with other miniaturized components such as microcontrollers, wireless radios, and antennae have led to the reduced power consumption of these loads directly as well as the savings that comes with mitigating the distinct system overheads of supporting each load independently. Their mere act of supporting so many system components with such little power inherently increases the value proposition of a given power solution since the same amount of power can now support more load, but SWaP is even further improved by enabling physically smaller power supplies to concurrently provide more power output (even while supporting wider input voltage ranges).

Three-dimensional power packaging (3DPP) is at the convergence of everything discussed in this blog [8]. Even with a slower pace of improving magnetic material properties, the overall performance and size of major magnetic constituents of power solutions have seen a dramatic improvement with the migration from wire-wound (often involving manual, hand-winding techniques) to planar magnetics that use finely controlled features to layout windings and integrate into the printed circuit assembly (PCA) with embedded magnetic core material. This enables even highly-complex magnetics structures to be integrated in a way that allows for tight process control (e.g., increased reliability) while concurrently taking advantage of manufacturing economies of scale to check just about every box in the SWaP-C checklist of goals. Figure 3 is an example of a cutaway in a point-of-load (PoL) converter that integrates a control/switch IC die, power magnetics, and module packaging into a compact solution that is optimized for space and thermally-enhanced for ease of heat spreading as well.

 

Figure 3. The 3DPP® Concept in RECOM’s RPX Series of Point-of-Load (PoL) Converters. Image used courtesy of Bodo’s Power Systems [PDF]

 

Getting Creative, While Keeping the Pace

Given the aforementioned point about the load (system) power budget on a much faster reduction trend than the increase of source (power solution) availability, the ability to keep on pace with Moore’s Law is far more attainable by putting the maniacal focus on reducing the system power budget than putting most of the engineering cycles into implementing a bigger power supply. This is where intelligent power management (IPM) techniques shine. IPM is a “combination of hardware and software that optimizes the distribution and use of electrical power in computer systems and data centers” [9]. This is more a frame of mind in design approach than anything else, so, for instance, changing the approach to power subsystem architecture from an “always on” to an “always available” mentality can bring paradigm shifts in the results of the end solution.

There is always a demand and use for increased energy density and cycle life FOMs for energy storage components. Like magnetics roadmaps, evolutionary improvement in (safe, practical) energy storage is closer to an order of magnitude off the pace of Moore’s Law. Even with that being the case, it does not imply a showstopper in helping the power keep the pace of system improvement (e.g., mostly SWaP-C) targets. The area where this is most apparent is when sizing the power solution to the worse case (in terms of demand, transient, temperature, manufacturing tolerance, safety margin, etc.) can provide a very wide spectrum of subjectivity in terms of finding the balance between meeting the needs of the system/application and not getting too out of hand in terms of overdesign. This point also really accentuates the importance and justification of careful characterization of loads before designing/implementing their respective power solutions. For instance, a system may have infrequent peaks of high-power draw, where most of the time is spent at a significantly lower, steady-state power level. It is highly wasteful (in terms of capital and operational expenditures (also known as CAPEX/OPEX) to engineer all the system’s power supplies, upstream distribution/holdup, etc., to those infrequent peaks when that demand can be met with some localized energy storage, therefore leaving the rest of the system to be optimized for that lower steady-state. This is the concept of peak shaving, which can be applied to any system from micropower to macro-power footprints.

Another variation of IPM is the utilization of load shedding/consolidation/allocation techniques. Nothing utilizes less power than something that is off, and nothing utilizes active power more efficiently than a load operating at the peak point of the load vs. efficiency curve of the upstream power solution. So, whether it means turning off power to subsystems when not in use (i.e., radio in a sleep state, dark silicon blocks of IC) or consolidating smaller loads that might otherwise require independent power supplies, this enables the implementation of effectively denser, more efficient power solutions. An example of intelligent power allocation can be in understanding a realistic scenario of external power needs, such as with universal serial bus (USB) or Power-over-Ethernet (PoE) ports that may be capable of sourcing more power as an aggregated peak (i.e., all ports operating at max power concurrently), but will not all be operating concurrently and therefore should not have an upstream power supply designed to source that aggregated peak.

Furthermore, it is uncommon for all system loads to be operating at their maximums simultaneously, so creating a system power budget by simply summing the maxima (e.g., data sheet worst-case maximums) of all loads is highly impractical in just about any use case. If possible, then disaggregating loads in a complex system to group them enables the optimization of their specific power subsystem(s) and, therefore, will lend itself to optimizing SWaP-C. This allows a design engineer to take advantage of the best of both worlds (Moore’s Law/MEMS and non-Moore’s Law/MEMS direct impacts).

 

Keeping Pace With Moore's Law

No one is kidding themselves by making the bold statement that all aspects of power solutions will keep a direct pace with Moore’s Law and the advancement of MEMS (soon to be referred to more often as nanoelectromechanical systems or NEMS) devices. As commonly depicted in industry news of the past several years, it hardly even seems clear Moore’s Law, itself, will continue (either in its existing form or something like it) into the foreseeable future. Even though this can create a gap between the source available power and the load power demand, it is not a gap that continues to grow exponentially and create an ever-widening chasm that makes power subsystems a reason to have to scale back system functionality

There are many creative techniques that power solution designers and system engineers use to keep pace to continue taking advantage of the technology enhancements Moore’s Law and MEMS provide regularly. IPM techniques are at the heart of this because we are being a lot smarter with every watt instead of a more rudimentary matching of the source to load in the traditional (e.g., worst-case peak) sense. Energy storage is also a highly underappreciated and underutilized tool in the toolbox of helping to meet full system performance expectations, both reliably and while maintaining a roadmap of reduced system size and increased power density.

At the end of the day, 3DPP and other advanced packaging techniques are really at the forefront of managing the gap between source and load because they are enabling more dramatic improvement to key FOMs than are seen purely in magnetics or energy storage devices.

 

References

[1] B. Zahnstecher, “Best Practices for Low-Power (IoT/IIoT) Designs: SEPARATING THE SOURCESIDE & LOAD-SIDE ANALYSES,” ECCE 2022 Tutorial, Detroit, MI, October 9, 2022.

[2] Wikipedia contributors, “Moore’s law,” Wikipedia, The Free Encyclopedia, https://en.wikipedia. org/w/index.php?title=Moore%27s_ law&oldid=1139518707 (accessed February 24, 2023)

[3] Wikipedia contributors, “Dennard scaling,” Wikipedia, The Free Encyclopedia, https:// en.wikipedia.org/w/index.php?title=Dennard_ scaling&oldid=1134445777 (accessed February 24, 2023).

[4] Wikipedia contributors, “Microelectromechanical systems,” Wikipedia, The Free Encyclopedia, https://en.wikipedia.org/w/ index.php?title=Microelectromechanica l_systems&oldid=1139870714 (accessed February 24, 2023).

[5] “Power Supply Design for maximum Performance,” RECOM Blog, Oct 21, 2022, https://recom-power.com/ rec-n-power-supply-design-for-maximum-performance-229.html (accessed February 15, 2023).

[6] “DC/DC for GaN,” RECOM Blog, Sep 16, 2022, https://recom-power.com/rec-n-dc!sdc-forgan-225.html (accessed January 23, 2023).

[7] E. Shelton, P. Palmer, A. Mantooth, B. Zahnstecher, G. Haynes, “WBG Devices, Circuits and Applications,” APEC 2018 Short Course, San Antonio, TX, March 4, 2018.

[8] “Introducing RECOM 3D Power Packaging® (3DPP®),” RECOM Blog, Feb 26, 2021, https:// recom-power.com/rec-n-introducing-recom-3d-power-packaging-%283dpp%29-145. html (accessed January 23, 2023).

[9] Data Center Facilities Definitions, “Intelligent Power Management (IPM),” TechTarget, https:// www.techtarget.com/searchdatacenter/definitions/Data-center-design-and-facilities (accessed February 24, 2023).

 

This article originally appeared in Bodo’s Power Systems [PDF] magazine

Featured image used courtesy of Adobe Stock