Glitch-Free Voltage Supervisor ICs — a Concept or Reality?

All the supervisor IC requires is a minimum voltage called power-on-reset (V_POR) before generating a clean or reliable reset signal. Before the minimum supply voltage, the state of the reset signal is undetermined.

 

Open-Drain Configuration

Push-Pull Configuration

Figure 1. An open-drain configuration and a push-pull configuration for reset topologies. Image used courtesy of Bodo’s Power Systems

 

Generally, we called this glitch on reset. There are predominantly two different topologies used for the RESET pin, open-drain and push-pull (Figure 1). Both topologies use NMOS as a pull-down MOSFET.

During power-up, if the supply voltage is below V_POR, there is not enough voltage for the internal circuitry driving the output MOSFET to operate so the output MOSFET is off. The supervisor has no way to control the output reset voltage. Reset will rise in proportion to the pull-up voltage (V_PULLUP), and once the supply voltage is above V_POR voltage, the internal MOSFET will drive the RESET pin to a valid state.

A voltage supervisor can be used to monitor the low-voltage rails for FPGAs, ASICs, or DSPs, where the voltage can be as low as 1V. In low-voltage processors, the I/O logic levels are very sensitive and the VIH can be as low as 0.5V as shown in Figure 3.

During power-up, FPGA, ASICs, or DSP needs to be in the RESET state until all the supply rails are stable. Since RESET may have a glitch when VDD is below V_POR, this glitch can trigger an unknown state of FPGA. Once VDD is above V_POR voltage, the internal MOSFET turns on, connects RESET to GND, and causes RESET to output the correct low logic level.

 

PARAMETER	SYMBOL	CONDITIONS	MIN	TYP	MAX	UNITS
INPUT VOLTAGE
Input Voltage Range	VCC	Operating range	1.7		5.5
		Reset output is guaranteed to be at known state	1.5			V

Figure 2. This is how a reset will rise in proportion to the pull-up voltage (VPULLUP) resulting in what is generally called a reset glitch. Image used courtesy of Bodo’s Power Systems

 

Figure 3. The interfacing of a supervisor with a low-voltage ASIC, FPGA or DSP. Image used courtesy of Bodo’s Power Systems

 

Figure 4. The power-on sequence with a glitch on reset. Image used courtesy of Bodo’s Power Systems

 

As the electronic industry moves towards low-voltage semiconductors, analog chip manufacturers are also working to deliver glitch-free supervisors with a conventional supervisor. Manufacturers can only reduce the V_POR voltage by improving the process, but a true glitch-free supervisor needs a new architecture.

Currently, system engineers use an external circuit with a conventional supervisor to mimic the glitch-free feature of the supervisor shown in Figure 5. By adding a standard JFET configured in a source-follower configuration, the voltage at the source will follow the voltage at VG minus the threshold voltage of the JFET. The threshold of the JFET causes approximately a 1V drop between VG and VOUT and eliminates the voltage potential rise on the output until the internal circuitry becomes operational.

 

Figure 5. A conventional supervisor with external P-JFEF for glitch-free operation. Image used courtesy of Bodo’s Power Systems

 

Figure 6. Application diagram of MAX16162 and a corresponding timing diagram. Image used courtesy of Bodo’s Power Systems

 

True glitch-free supervisors can sink the current through a reset, which forces reset to a ground potential even at zero VCC. Figure 6 shows an example of a true glitch-free supervisor in a circuit. The MAX16161/MAX16162 does not require any external components for its glitch-free operation, which makes them tiny and cost-effec - tive.

Summary

A true glitch-free supervisor IC is no longer just a concept. Design - ers now have a supervisor IC that generates a reliable reset signal at zero supply voltage to enable system engineers to use the IC to monitor low-voltage (less than 1V) electronics. The MAX16161/ MAX16162 supply a tiny, nanoPower IC and use just 825nA of qui - escent current to help extend system battery life.

 

This article originally appeared in Bodo’s Power Systems magazine.