Exclusive Interview: How Embedded Silicon Capacitors Enable AI Power Integrity

As artificial intelligence (AI) and high-performance computing (HPC) applications scale exponentially, data center power delivery architectures face unprecedented hurdles. Hardware engineers are intensely focused on maximizing the critical performance-per-watt metric for power-hungry processors like GPUs, TPUs, and NPUs.

To explore how next-generation passive components are solving these power integrity challenges, EEPower spoke with Mukund Krishna, Senior Manager of Product Marketing at Empower Semiconductor, to discuss the evolution, design considerations, and applications of embedded silicon capacitors (ECAPs).

The Genesis of Silicon Capacitor Innovation

EEPower: What was the motivation for Empower Semiconductor to invest in silicon capacitor technology?

Mukund Krishna: Empower's primary focus is on high-density and high-performance integrated voltage regulators (IVRs) focused on solving the most pressing challenges for the highest performance processors. These include, but are not limited to, high-performance computing accelerators and xPUs like GPUs, TPUs, NPUs, etc.

One of the biggest challenges during the early development of IVRs was selecting the correct passive components, stemming from the need for a much higher frequency response, which led to the development and investment into silicon capacitors. Fast-forwarding to now, all our IVR products encompass silicon capacitors in varying degrees and are an integral part of our solution.

As Empower gathered expertise on the development of silicon capacitors, we made them available as an independent product portfolio called ECAPs, since it turned out that our customers faced the same challenges for high-frequency decoupling, driven by the accelerated use of ultra-high-performance processors.

Silicon capacitors offer improved power and signal integrity for advanced computing systems. Image used courtesy of Empower Semiconductor

This further drove focused investment into our ECAP product line, where we now have a portfolio of high-density and ultra-low-impedance products focused on substrate-integrated solutions. They now have excellent traction with major xPU/ASIC manufacturers and are complementary to our IVR solutions.

Solving the Power Integrity Puzzle for AI

EEPower: What unique problems do embedded silicon capacitors (ECAPs) solve for high-performance computing and power delivery?

Krishna: ECAPs and silicon capacitors in general feature the unique combination of high density (µF/mm²) and low impedance (ESL), enabling system engineers to achieve the most optimal power integrity for their system. The ultimate goal for a data center built with the high-performance AI xPUs is to achieve the highest performance/watt metric. While the xPUs themselves address the performance piece, the focus here is on reducing the power used to achieve it.

A critical factor in that power usage is the power supply voltage level, which would need to be operated at the lowest allowable level. However, a practical system has a power delivery network (PDN) from the voltage regulators (VRs) through the main PCB and package to the xPU die, with various banks of capacitors in between. Higher noise on the PDN results in needing a correspondingly higher supply voltage. Hence, careful optimization of the PDN is required to minimize this noise.

Embedded silicon capacitors are uniquely able to be located much closer to the xPU die (resulting in lower connection/mounting impedances) and feature very low parasitic impedances, especially at high frequencies. Hence, they greatly ease PDN optimization and can reduce noise by over 2x, ultimately enabling a lower supply voltage level. A lower supply voltage of even 50 mV can reduce power usage by 15%, enabling a higher performance/watt metric. Multiplied across hundreds of thousands of processors, this can have a profound effect on the energy usage and performance-to-power metric.

Key Design Considerations for SI/PI Engineers

EEPower: What key design considerations do engineers need to look at when migrating their designs to employ your silicon capacitors?

Krishna: The critical goal of the SI/PI engineer is to optimize the PDN—specifically to ensure the optimal power integrity. The design process starts with determining the level of tolerable noise (also called droop) for a target load step. At high frequencies (between the 10s to 100s of MHz), this leads to a target capacitance value. This provides the guidance for what is required to be mounted on the "landside" or embedded in the package substrate.

Silicon capacitors can be embedded in the package substrate or mounted on the landside. Image used courtesy of Empower Semiconductor

The mounting impedances for these choices will also have to be considered, corresponding to the mounting locations. Factors in deciding the mounting locations are mechanical constraints such as allowable space and height. The size of the package substrate used for embedding, number of layers, core thickness, and ability to stack the embedded silicon capacitors are other factors that are to be considered. This information, in conjunction with the required capacitance from the previous analysis, leads to the density requirements.

ECAPs, like many other silicon capacitor products, are available in a range of form factors and densities. The magnitude of capacitance, and the density requirements from the aforementioned analyses, can be used to select from a portfolio of available capacitors. In many cases, some degree of customization may be required. ECAPs can be customized at many different levels, such as bump or pad heights, bump compositions, die/silicon thickness, form factors, number of terminals, and their pitch to suit the specific requirements. This high degree of customization, combined with their superior stability and ultra-low impedance, makes them an ideal tool in the SI/PI engineer's toolbox.

Shifting Decoupling to the Start of the Design Cycle

EEPower: Traditionally, adding power supply decoupling capacitance occurred near the end of the design cycle. Does that change when incorporating ECAPs?

Krishna: It definitely changes the approach. ECAPs are critical in ensuring power integrity at high frequencies (from 10s to 100s of MHz) and, therefore, need to be located in close proximity to the processors in question. This is a critical change from previous approaches of incorporating decoupling at the final stage as a "band-aid" approach, stemming from the exponential increase in performance in xPUs and the corresponding need to squeeze the highest performance/power metric.

ECAPs are also exceptionally stable to voltage and temperature variations, allowing a definitive and reliable plan at the start of the design cycle to address power integrity on the package.

Once this is done properly, the PCB-level decoupling can still be addressed at a later stage of the design cycle. However, most systems being designed today are incorporating the plan for the entire PDN, including the VRs and PCB-mounted decoupling, at the start of the design cycle to ensure a tightly knit power integrity solution.

Broadening the Horizon Beyond HPC

EEPower: Besides AI and HPC processors, do you see other applications that could benefit from ECAPs?

Krishna: In general, any application that drives high performance and results in the need for power integrity optimization at high frequencies can utilize ECAPs. For example, ECAPs have already been utilized in mobile phone SoC applications where a landside-mounted ECAP has led to lower supply voltage noise, higher performance, and better battery utilization.

Other examples of applications that are driving such performance levels are FPGAs, DSPs, and custom ASICs used in high-performance networking, optical communications, and edge computing.