Silicon capacitor supports new power distribution networks performance requirements
Murata high-density silicon capacitors are developed with a semiconductor MOS process and are using the third dimension to substantially increase the capacitor surface and thus its capacitance without increasing the capacitor footprint.
Murata has extended its product offering for the mobile and high-performance computing (HPC) markets with the availability of its latest silicon process technology to fabricate silicon capacitors with a density of 1.3µF/mm². The extremely low ESL (few pH) and low ESR (few mΩ) of these devices support the highest performances of new power distribution networks (PDN) that require low impedance over a wide frequency bandwidth.
Image used courtesy of Murata
As digital ICs evolve to offer more features at lower voltages, resolving issues like noise and voltage fluctuation is critical. Its <40µm profile enables chip designer engineers to embed the silicon capacitor into the package as close to the active die as possible, minimizing the current’s effective path length and, thereby, minimizing parasitics.
These multi-terminal devices satisfy the various SoC and microprocessor design requirements for multiple terminal capacitor networks. Replacing conventional monolithic ceramic capacitors with multi-terminal silicon devices reduces the total quantity of capacitors required on the board significantly, which improves the compactness of the end design. Fewer capacitors also result in total savings in both bills of materials and mounting costs.
