Power Stack Reference Design for Inverter-Based Resources

This article is published by EEPower as part of an exclusive digital content partnership with Bodo’s Power Systems.

In recent years, demands for power semiconductors, key devices for contributing to realizing a decarbonized society, have been rapidly expanding. The reason is that the path toward renewable energy grids involves significant integration of inverter-based resources (IBR), composed of many small IBRs that adjust frequency and voltage to obtain higher system performance. Therefore, wind power (WP), photovoltaics (PV), hydrogen, and energy storage systems are expected to grow significantly. The power rating of a large inverter for WP or central PV inverters could be approximately 10 MW. The key manufacturers design the utility-scale solutions using 1.5 MW to 2.5 MW with paralleled connections to achieve the required output power. To reduce customers’ developed workload, Mitsubishi Electric has provided a single-phase inverter solution composed of 3 paralleled industrial IGBT modules in the LV100 package.

Image used courtesy of Adobe Stock

The LV100 has a footprint of 100 mm × 140 mm. It has become popular for high-capacity inverter systems as shown in Figure 1. The stack design includes the evaluation and selection of various other components. Moreover, current balancing, skin effect, and temperature rising, as for example, need to be considered. Moreover, to verify the electro-thermal design under different cooling conditions, both liquid and forced-air cooling could be suitable for the power stack by changing the heatsink. This article introduces the performance and key thermal design information of the power stack, and its specification as listed in Table 1. Hence, the maximum current is designed to 1800 A for a 3-phase connection to achieve 2 MW of output power, and the current imbalance ratio could also be controlled within 5%.

Figure 1. Illustrate of power stack and technical points. Image used courtesy of Bodo’s Power Systems [PDF]

Design Methodology and Power Stack Output Capacity

The proposed power stack is designed by electro-thermal co-simulation using computer-aided engineering (CAE) software: Q3D and Workbench, Ansys. There are two steps for evaluating the output capacity of the power stack as shown in Figure 2, the ambient and water inlet temperatures are set at 25°C, and heat generating of DC capacitors is not considered. In step 1, thermal evaluation was done under 1800 A of DC current, and temperatures at the DC busbar and IGBT case (T_c,x) were measured.

Figure 2. Thermal evaluation methodology of power stack. Image used courtesy of Bodo’s Power Systems [PDF]

Wherein, the T_c,1 and T_c,2 represent baseplate temperature just under high- and low-side IGBT chip, respectively. Heat-transfer coefficient (HTC) for simulation was adjusted to meet with experimental results for achieving less than 10% error. In step 2, loss of DC busbar and IGBT modules was simulated considering space-vector pulse-width modulation (SVPWM) (by power loss calculator, Melcosim made by Mitsubishi Electric. Condition: VDC = 1100V, Modulation index = 0.9, Power factor = 0.95, 2.5kHz). Wherein, the thermal model is the same as step 1 and the chip junction (T_vj) was calculated from thermal resistance and simulated T_c. Then the temperature distribution under inverter mode could be estimated.

Table 1. Specification of power stack.

Figure 3 shows the estimated output power under inverter conditions for air and liquid cooling by setting different conditions of generating loss and HTC, the solid and dot lines represent the T_vj and busbar temperature T_busbar, respectively. The output power of 2 MW could be achieved for liquid cooling. Air-forced cooling results in an output power of 1.4 MW with a gentle temperature rising of the busbar.

Figure 3. Relationship between T_vj and T_busbar under different output power and cooling methods. Image used courtesy of Bodo’s Power Systems [PDF]

Stack Performance Improvement

For MW-level power stack design, the power modules are usually used in parallel connection while considering current balancing, driving synchronization, short circuit protection and temperature rising. The design concept of current balancing is to equalize the impedance among parallel paths proposed in this article focuses on the temperature rise of components while explaining the heat dissipation under different design approaches.

1) Bridge width effect of DC busbar

Figure 4 shows experimental results of temperature distribution with different bridge widths of DC busbar under 1800 A of DC current and 3 mm of layer thickness. In doing so, the 20 mm of pitch distance among paralleled IGBTs is fixed. Since IGBT modules dissipate heat via the heatsink and the DC busbar, a narrow bridge width causes higher IGBT temperature due to an increase in thermal resistance.

a) Bridge width = 34 mm. Image used courtesy of Bodo’s Power Systems [PDF]

b) Bridge width = 24 mm. Image used courtesy of Bodo’s Power Systems [PDF] 

Figure 4. Temperature distribution under different bridge widths.

2) Flow direction of forced-air cooling

In forced-air cooling, the flow direction affects significantly the system performance. Each IGBT module should receive equal airflow to achieve minimum temperature imbalance in parallel conditions. Hence, the air-flow direction of the proposed power stack could be separated into two cases as shown in Figure 5. In case 1, forced air flows through the heatsink and gets heated up by the IGBTs. Afterward, the warm air flows to the DC busbar and the capacitors. The front-side IGBT whose case temperature is T_c2 receives maximum cooling flow, but the cooling of peripheral components and even the back-side IGBT whose case temperature is T_c1 become worse due to higher ambient temperature. Whereas, the airflow direction of case 2 would be better with considering system performance.

a) Case 1. Image used courtesy of Bodo’s Power Systems [PDF]

b) Case 2. Image used courtesy of Bodo’s Power Systems [PDF]

Figure 5. Different air-flow directions for power stack (side view).

Study Results

This study indicates influence factors on temperature rising: DC busbar and direction of airflow. The thermal management is a cross-coupling issue. Hence, the design and selection of peripheral components should be optimized. The IGBT modules with LV100 package are a suitable solution for such a power stack due to their easy paralleling and low inductance. This reduces design difficulty for achieving better system performance on thermal management, current balancing, and lower voltage spike. Especially, the symmetric chip layout simplifies the heatsink design and reduces the thermal cross-coupling between IGBT modules. The line-up of the LV100 package is shown in Table 2. LV100 for industrial applications covers voltage ratings of 1200 V, 1700 V, and 2000 V. The package is based on the SLC packaging technology with a thermal cycle failure-free packaging technology by matching thermal expansion coefficients. An LV100 package for railway applications is available for 1700V and 3300V and uses an MCB baseplate.

Table 2. Line-up of IGBT module with LV100 package. Image used courtesy of Bodo’s Power Systems [PDF]

This article originally appeared in Bodo’s Power Systems [PDF] magazine and is co-authored by Zheng-Feng Li, Nobuya Nishida, Mitsubishi Electric Corporation, Fukuoka, Japan; and Koichi Masuda, Nils Soltau, Mitsubishi Electric Europe B.V., Ratingen, Germany.