Increased Power Density and Performance with 3D Embedded Substrate TechnologiesOctober 28, 2015 by Brian NarvesonErnie Parker
This article discusses the investigation done by PSMA and offers the important core technologies required for embedding substrates.
The Driving Force Behind Finding New Power Packaging Techniques
Power source suppliers are continually being asked to deliver more power in the same footprint. This challenge has hit a fever pitch as digital semiconductor packaging technology has increased performance with wafer stacking through the use of wafer thinning and through-silicon-via (TSV) technology. In addition, the introduction of 2.5D and 3D integration has facilitated heterogeneous (“More than Moore”) integration.
Use of this technology is increasing as conventional die shrinking has hit a “cost barrier” brought about when advanced deep-submicron semiconductor technology could no longer reduce cost with the addition of more functions to the semiconductor die. Digital 3D packaging and integration allows the power requirements of the digital load to increase two to five times, within the same footprint, in a single generation. Now, the power industry is tasked with finding new ways to package power sources that will meet this demand without increasing footprint.
In parallel, the power semiconductor technology is facing a “construction barrier” that prevents the realization of the significant benefits of the new technology can offer in terms of increased power efficiency and higher power density. These new technologies, including gallium-nitride (GaN), silicon carbide (SiC), and gallium-arsenic (GaAs) power semiconductor devices, all require operation in a package that is free of bond wires and that minimizes parasitic interconnect elements. Both of these challenges can be addressed with power packaging that utilizes embedded substrate technologies.
Investigation of Power Package Solutions
In order to investigate this technology, the Power Sources Manufacturing Association (PSMA) commissioned a report “Current Developments in 3D Packaging with Focus on Embedded Substrate Technologies” that is related to packaging design. The 340-page report, prepared under contract by LTEC Corporation with a subcontract to Anagenesis, Inc., and Fraunhofer-Institute was published in March 2015. It is based on the extensive research of over 750 articles and papers and by conducting 30 industry expert interviews.
For the purpose of this article, the following definitions apply:
- Embedded substrate technology is defined as the inclusion of at least one active or passive electrical component within the top and bottom conductive layers of a substrate.
- A substrate is defined as a planar structure having multiple conductive and insulating layers.
Fig. 1 provides an example of this technology illustrating a Sarda Technologies 12 V input, 16 A output, 5 MHz heterogeneously integrated power stage using 3D packaging with embedded substrate technology.
As part of the project, 30 companies were surveyed to determine why they were actively producing or developing power sources utilizing embedded technology and at what power level they were considering utilizing this technology. The survey found the overriding reasons for using this technology was to reduce size (increase power density) and improve performance. It also found development activity at power levels up to and exceeding 1000 Watts.
Figure 1: PCB-embedded two-phase power stage with GaAs FET quad (Courtesy of Sarda Technologies Inc.)
The Core Technology for Embedding
The core technology required for embedding is a PCB or inorganic substrate. Europe is leading in high-volume, commercially-viable embedded substrate manufacturing technology. This success was enabled by research projects funded by the European Union’s sixth and seventh framework programs (FP6, FP7).
The first, “HIDING DIES” (FP6), developed the fundamental technology for chip-in-polymer packaging based on embedding thinned silicon in resin coated copper (RCC) dielectric followed by laser drilling of via holes to the chip contacts and to the substrate and finally metallization of vias and conductor lines. A follow-on project “HERMES”, under FP7, focused on bringing the technologies into real manufacturing PCB production. AT&S leveraged its involvement with these programs to develop their large panel-based PCB process known as Embedded Component Packaging (ECPTM).
The AT&S ECP™ process is depicted in Fig. 2. AT&S manufactures on 18 in. x 24 in. panels have shipped over 100-million units and claims > 99% yield. Their process is used by GaN Systems and Texas Instruments for embedding of their semiconductor devices.
An overview of several of the processes available for making embedded substrate power assemblies are listed below, and the details and additional processes can be found in the report.
TDK-EPC Corporation has developed its own process named Semiconductor Embedded in Substrate (SESUB™). Their embedded process is suitable for high-density power supply modules or subsystems, either as substrates or interposers, with or without over-molding. A benefit of SESUB™ is the ability to have complete metal shielding of the package, an attractive feature for Electromagnetic interference (EMI) .
General Electric has been a pioneer in recognizing the benefits of component embedding and in technology development, beginning with technology for chip embedding in the 1990’s. GE’s Power Overlay Technology (POL), is backed by a strong portfolio of over 300 patents. GE is actively engaged in licensing its technology.
Figure 2: AT&S Embedded Component Packaging (ECP™) Process Flow
Infineon developed a variant of the AT&S process that is similar to TDK-EPC’s SESUB™ and have used it in their Dr. Blade™ product family.
Schweizer AG’s P2-PAK process, shown in figure 3, was an early entrant with embedding developed as an alternative to expensive direct-bond-copper (DBC) for high current inverters, converters, industrial motor drives, and automotive applications.
Figure 3: Schweizer P2-PAK Process
Additional processes from Fujikara, Shinko, Wurth Electronik, and Semikron are covered in the technology report. Japan and Korea tend to have a leadership position in fine pitch high-density, low-power technologies, while European companies have a leadership position in embedding power electronic components.
The Availability of Components Affects Embedding
The second key technology for embedding is the availability of components. There are two classes of embedded components:
- First, there is a discrete device, termed the “inserted” component. In this case, the surface mount passive device, R L or C, is manufactured prior to assembly in the printed circuit board. Usually, these are mounted in laser machined cavities within the PCB. Semiconductor devices are also inserted and connected to the substrate using a variety of techniques.
- Second, there is a “formed” component that is manufactured as an element(s) within the PCB. All three types of passives (resistors, capacitors, and inductors) can be formed in an embedded substrate. Figure 4 illustrates the various types of embedded components and Figure 5 shows how they can be implemented as a PCB substrate.
Figure 4: Embedded Components
Figure 5: Example of an embedded assembly
The ability to execute an embedded power design is very dependent on the availability of insertable passive components, optimized for PCB embedding purposes. The report devotes individual chapters to resistors, capacitors, and inductors. Availability of power devices is still somewhat limited in terms of form factor and terminal metallurgy but the number of sources is expanding rapidly. The report also provides lists of vendors with production parts available now.
Successful transition to full volume manufacturing depends on advances in supply chain and technology for compatible passive component technologies. While this article focused on embedded substrate component technology, the 3D Embedded Substrate Technology report also covers the current state of the art as well as challenges and constraints in semiconductors, passive components, high temperature die-attach, interposers, thermal management, packaging technologies, additive manufacturing, and laser fabrication, all of which will play a role in the success and timing of a transition to 3D power packaging.
IPC Standards for Embedded Substrate Technology
Another sign of the maturing of embedded substrate technology is the number of standards completed and being written. The IPC has published embedded standards for, resistors (IPC-4811), capacitors (IPC-4821), printed circuit board design (IPC-2316) and materials (IPC-4101) plus one being written on design and assembly processes (IPC-7092). The substrates, components, and manufacturing processes are available and being developed to meet these standards. There is more elaboration provided regarding standards in the report.
The Groundwork for Power Packaging's Future has Been Laid
There has been substantial progress and excellent opportunities lie ahead for the power electronics and semiconductor industries, and the entire manufacturing ecosystem to embrace PCB embedding and 3D packaging technologies for power electronic applications. The intersection of these technologies with the merging wide-bandgap power semiconductor technology creates truly exciting possibilities. These technologies, combined with wide-bandgap semiconductor devices will literally revitalize the entire power electronic infrastructure for the twenty-first century.
The PSMA reports on 3D packaging are provided free of charge to PSMA members.
PSMA is a non-profit professional organization with the objective of enhancing the stature and reputation of its members and their products, and improvement of their technological power sources knowledge. Its aim is to educate the electronics industry, academia, government, and industry communities as to the applications and importance of all types of power sources and conversion devices.