New Industry Products

SiC Power MOSFET Gate Drive Evaluation Platform

February 03, 2019 by Paul Shepard

The Gate Drive Evaluation Platform (GDEV) from Littelfuse was designed to demonstrate the continuous operation of Littelfuse SiC power MOSFETs and diodes in a half-bridge configuration. In addition, it provides a well-defined testing environment for evaluating and comparing the performance of various driving board designs, as well as driver ICs.

The GDEV system consists of a motherboard that gate driver module boards can be plugged into quickly and easily. The modular gate driver boards and simplified interface strategy were chosen to optimize the functionality of this platform.

A full thermal management solution - via an integrated heatsink - allows for continuous operation of the power devices under rated voltage and current conditions. The GDEV can be used to:

  • Evaluate continuous operation of SiC power MOSFETs and diodes under rated voltage and rated current, delivering real power to the load
  • Analyze system-level impacts associated with SiCbased designs
    • Efficiency improvements
    • EMI emissions
    • Passive components (size, weight, cost)
  • Compare the performance of different gate driver solutions under well-defined and optimized test conditions
  • Test gate driving circuits under continuous working conditions to evaluate gate driver thermal performance and EMI immunity

The GDEV leverages a half-bridge configuration with gate driver module connections for both top and bottom devices. It performs as a power stage reference design that allows users to test the performance of SiC MOSFETs and diodes under continuous switching conditions at high voltage and high current levels, delivering real power to the load.

It also provides a well-defined and standardized testing environment for evaluating and comparing the performance of different driving board designs with different driver ICs. The power stage features a half-bridge configuration with the option to use a SiC power MOSFET, SiC Schottky diode, or both in parallel for each switch position.

The power loop PCB layout is optimized to minimize loop inductance and coupling between the power and gate loops. A probe-tip adapter allows for accurate drain-source voltage measurements.