National Semiconductor Introduces Second-Generation PowerWise Technology Energy Management Unit and Advanced Power Controller
National Semiconductor Corp. announced its second-generation, digitally-programmable LP5552 PowerWise® energy management unit (EMU) and advanced power controller (APC2) intellectual property (IP) package for reducing power consumption in battery-powered handheld consumer products. National's APC2 IP pairs with the LP5552 EMU to reduce the power consumption of high data-rate digital processors with frequency-scaling capability by up to 70%. The APC2 IP is compatible with Intelligent Energy Manager (IEM) frequency-scaling technology from ARM Ltd. The LP5552 and APC2 are compliant with the PowerWise Interface™ (PWI) 2.0 open-industry standard introduced by National Semiconductor and ARM earlier this year.
National's LP5552 enables a digital processor to adaptively adjust its supply voltage to the minimum level needed, greatly reducing its power consumption. The LP5552 includes two adaptive-supply-voltage buck regulators for the processor cores and five additional programmable regulators. The linear regulators power the input/output (I/O) ring, oscillator and phase-locked loops (PLL) and embedded and external memories on low-power SoCs, and can also power other auxiliary devices in the system. The PWI 2.0 interface controls the LP5552's functions for simple interfacing to the digital processor.
Compliant with the AMBA™ specification, National's APC2 is a synthesizable macro-cell that includes a hardware performance monitor to support adaptive voltage and frequency scaling. Similar to the APC1 announced by National Semiconductor in 2004, the APC2 automatically calibrates for process and temperature variations, and communicates with the LP5552 using the PWI 2.0 interface. In addition, the APC2 concurrently manages multiple voltages and frequency-scaled power domains on a feature-rich multi-processor SoC, as well as bias voltages for leakage reduction with threshold scaling.
The LP5552 supports the PWI 2.0 interface, a 2-pin, high-speed serial power management control interface for advanced processor power management. To enable adaptive voltage scaling, the LP5552 includes two digitally-programmable, 600mA, 0.6 to 1.2V buck regulators with up to 90% efficiency and excellent transient performance for rapidly varying digital loads. In addition, it has five programmable low drop-out (LDO) regulators with output voltages ranging from 0.6 to 3.3V. The linear regulators support output current ranges from 50 to 250mA. Two of the linear regulators contain a low quiescent (lq) current-retention mode for minimizing system power consumption when SoC processors are inactive, but need fast recovery time. Available in a lead-free, 36-bump micro SMD package, the LP5552 has excellent package thermal characteristics and operates over the full temperature range from -40 to +85°C, with input voltages from 2.7 to 4.8V.
The APC2 controls voltage in modern, multi-core processor ICs. The APC2 is embedded in SoC devices such as digital baseband and application processors used in portable applications. The APC2 is provided as configurable soft intellectual property with RTL, configuration and synthesis scripts, test benches, implementation and programming documentation, as well as reference driver software. The IP package is compatible with industry-standard design tools and flows. The APC2 supports up to four power domains each with up to four independently frequency-scaled clock domains inside. It also supports eight frequency settings, clock stop and power down modes for each clock domain. The APC2 includes a PWI 2.0 compliant master interface to the peripheral devices as well as AMBA advanced peripheral bus (APB) host interface for configuration and control. The APC2 supports deployment of both table-based dynamic voltage scaling and PowerWise adaptive voltage scaling.
The LP5552 is available now and is priced at $5.50 in 1,000-unit quantities. The APC2 is available for licensing from National and ARM.
