SWaP Benefits to Reduce Power Consumption in High Reliability Microprocessors

Despite the rising power efficiency of new processors, the accelerating demand for computational power often outstrips the ability to cool the systems down and/or to provide them the right amount of current. Furthermore, mechanical/thermal design usually happens late in the development cycle. Consequently, it is likely to run up against thermal limits late in the design process. Designers naturally want to optimize their systems and find acceptable tradeoffs.

Teledyne e2v High-Reliability Microprocessors have been the workhorses across a broad range of defense, aerospace and other high-reliability markets for several decades now. Today, contemporary processor advancement is driven by the demands of other future mass markets such as the extreme number crunching needs of autonomous driving. Thus, the changing economic focus of suppliers, like NXP, has deep consequences for high-reliability supply chains. Not least, those products are engineered with less stringent requirements for many applications.

Teledyne e2v, building on its long-term strategic relationship with NXP, is uniquely positioned as a trusted supplier of customized processor options. Customization is possible based on either the power architecture (e.g. T series processors such as the T1042) or ARM architecture (e.g. Layerscape LS1046).

 

Image courtesy of Teledyne e2v

 

SWaP Minimization — Three Degrees of Optimization

Meanwhile, SWaP (Size, Weight, and Power) minimization persists and informs daily decision making of high-reliability system designers working with harsh environments, even space. After all, processors are a strategic component choice representing a large contributor to the total power budget (the P of SWaP). Equally, thermal dissipation drives heatsinking, impacting upon system size and weight goals (the S & W of SWaP). In many cases, selecting one or even a combination of three degrees of customization can deliver significant value to the design.

 

Approach 1: Power consumption optimization

Power consumption optimization for a specific customer use case consists of characterizing the processors versus the customer application, prior to selecting those with the lowest total power consumption. It starts with evaluating a population of target components, taking test data, and examining the power consumption spread. Ultimately the purpose is to select out only those devices exhibiting the best power consumption characteristics for a given application use case.

Power screening evidence suggests that for some applications when the use case is clearly defined, it is possible to operate a processor well within its operating envelope. However, this requires knowing with greater precision, how the device behaves within the target use case. There is no quick answer to this, but power screening provides the detailed analysis necessary to reach a definitive understanding. In one project, Teledyne e2v demonstrated its ability to source processors with power consumption 46% lower than the worst-case standard product scenario as illustrated in Figure 1, and this by combining characterization of the customer’s application and power screening. Here, a device initially believed unsuitable for the task due to assumed excess power consumption, could now be sourced and designed-in with confidence.

 

Approach 2: Custom packaging

Alternative custom package selection for thermal resistance optimization, which in most cases brings circuit/die protection as well: modify-ing or redesigning the existing standard product package to lower its thermal resistance from junction to board, or junction to package top:

• Can be used to reduce the junction temperature, thus lowering power consumption (assuming the same heatsink remains in place). Alternatively, it reduces the cooling system (size/weight) since the package thermal resistance (Rth) is lower, that of the heatsink can be larger.
• An alternative package can enhance vibration protection for the component and/or simplify and improve the thermal interface between the cooling system and the processor.
• To deploy a lid or not to further impact thermal performance.

A lid is a cover that is found on most processors which acts as a heat spreader and protection for the component’s die. However, depending on the application, some designers might want a lid to help integrate a heatsink more easily. Others prefer a lidless design because they can’t accept the extra thermal resistance of the lid. Also, note that a lid dramatically reduces the junction to board thermal resistance, a clear benefit if it is desired to conduct more heat through the printed circuit board (PCB).

Some components are delivered with lids (e.g. LS1046), others come without (e.g. T1040). Usually, the designer doesn’t have a choice because with ‘commercial off the shelf’ (COTS) components, both versions are rarely available. That’s where Teledyne e2v has the flexibility to help, by proposing to add or remove a lid.

 

Approach 3: Extended (i.e. >125°C) junction temperature

Raised maximum junction temperature (TJ) specification can extend operation. This requires additional qualification work at elevated temperatures combined with careful consideration of operating life profile. The key point is to quantify this since elevated temperature operation affects device failures in time (FIT rates).

This optimization step considers the viability of operating silicon beyond conventional thermal limits of commercial, standard products. Certainly, silicon is not physically limited to operate only up to 125°C, several elevated temperature applications exist and are already served. The benefit of higher junction temperature operation is the extra thermal headroom on offer. But elevated temperatures have an implied penalty namely significantly raised power dissipation. Where a higher junction temperature can pay off is in applications with an operating profile requiring short bursts of increased dynamic power, yet it is critical these bursts can be handled within the thermal capacity of the design.

 

About the Author

Roland R. Ackermann has been a technology journalist since 1957, covering electronics, engineering, and manufacturing/automation. He has been a freelance journalist 1996, publishing work in Elektronik Journal, was editor in chief of Electronik Embedded System and verlagsweltMAGAZIN, and also wrote numerous articles in German and English publications and newspapers. He was a regular column writer in E&E Faszination Elektronik and is now a correspondent for Bodo's Power Systems. Ackermann holds talks at international venues, moderates panel discussions, and organizes events.