Technical Article

Interpreting and Validating Dynamic Characteristics for Wide Bandgap Power Device Data Sheets

January 28, 2021 by Ryo Takeda

This article discusses practical considerations for the measurement and extraction of dynamic power semiconductor parameters.

Do you find it frustrating trying to measure dynamic characteristics of WBG devices and correlate them with published data sheet results? With the advent of Wide Bandgap (WBG) devices, older test methods and standards don’t address the capabilities of these new semiconductor technologies. Therefore, you see so many ‘typical’ specifications used in data sheets for WBG devices. In this article, we will provide some practical considerations for measurement and extraction of dynamic power semiconductor parameters, which can offer explanations to correlate measured results and data sheet results.

In previous articles, we’ve described many of the challenges to obtain repeatable and reliable dynamic measurements and extractions from your Double Pulse Test (DPT) systems. As designers of power converters, it is also important to be able to correlate data sheet dynamic specifications with the results obtained by measuring and characterizing power devices. There are many dynamic characteristics given in Silicon Carbide (SiC) and Gallium Nitride (GaN) power device data sheets. We will focus on switching characteristics [td(on), tr , E(on), t d(off), tf , E(off)] and reverse recovery characteristics [trr, Irrm, Qrr]. Gate charge parameters and Rds(on) measurements and extractions will be discussed in later articles.


Switching Characteristics

Figure 1 shows typical switching characteristics from a 1200V SiC MOSFET datasheet.


Data Sheet Switching Characteristics. (source: page 2, C3M0021120D Datasheet – Rev. -, 08-2019)
Figure 1: Data Sheet Switching Characteristics. (source: page 2, C3M0021120D Datasheet – Rev. -, 08-2019)


The first thing to determine is the DPT setup and test conditions. Because DPT setups are not standardized, the device manufacturer will typically show a simplified diagram of the test setup (Figure 2).


Simplified DPT Setup. (source: Fig 3-1: SCT2080KE Datasheet - 2015 ROHM Co., Ltd.)
Figure 2: Simplified DPT Setup. (source: Fig 3-1: SCT2080KE Datasheet - 2015 ROHM Co., Ltd.)


There are many things to consider when comparing your DPT setup with the manufacturer’s setup.


What device is used for the ‘high side’ in the DPT setup?

The purpose of the high-side device is to ‘freewheel’ the current stored in the inductor during the off state, allowing the current to immediately flow through the DUT as the second pulse begins. Either the same device (denoted: Body Diode FWD in Figure 1), assuming a body diode is present, or a simple diode (denoted: SiC Diode FWD) is used. Because the output capacitance (Coss/Cds) of the ‘high side’ device will resonate with the power loop inductance during turn-on, it is sometimes advantageous or necessary to use a simple diode to get clean enough waveforms to extract the switching parameters. In addition, the reverse recovery current (Irrm) of a high side device will add to ID at the beginning of the second pulse distorting the DUTs switching performance (i.e. increasing the turnon switching losses).


Is the switched load resistive or inductive?

Older switching tests were often done with resistive loads. With the advent of IGBTs and WBG devices, higher frequency switching creates more challenges for the designers. Inductive loads more accurately simulate real loads (e.g. motor windings) and have become the norm for switching characterization. Sometimes the load inductor (e.g. L = 65.7µH) is mentioned in the test conditions. This load inductor is used to provide the specified current, ID and is not part of the power loop.


What operating conditions are used to test the device?

In the example in Figure 1, one sees the typical specified parameters:

  • VDD/VDS = 800V
  • I D = 50A
  • RG(ext) = 2.5Ω
  • VGS = +15/-4V
  • Temperature = 25˚C/175˚C


What is rarely, and if so briefly, included in the test conditions, are the parasitic impedances in the DPT system (Figure 3). These parasitics have significant impact on the performance of the DPT system to provide accurate characteristics of the DUT. If the DPT system designer doesn’t consider these parasitics, the measured waveforms are often measuring the characteristics of the DPT system in addition to the characteristics of the DUT. Therefore, these parasitics are often the reason for discrepancies between measured results and data sheet results, even if the other test conditions are consistent between your DPT system and the data sheet.


DPT Diagram with device and system parasitics.
Figure 3: DPT Diagram with device and system parasitics.


As we’ve mentioned in previous articles, it is difficult to measure these parasitic impedances. However, there are some common ways that the industry uses to determine the power loop inductance (LPL = LPL1 + LPL2 + Lshunt). One method is to extract LPL by using the simple formula for the voltage across and inductor (V = L * di/dt), solved for L (L = V/(di/dt)). By taking the measurements of V, di/dt from the first dip in VDS during a turn-on event, one can calculate the approximate LPL for the DTP system (Figure 4).


Parasitic power loop inductance (LPL = 87.27V/ (16.16A/6.43ns) = 35 nH) extraction.
Figure 4 – Parasitic power loop inductance (LPL = 87.27V/ (16.16A/6.43ns) = 35 nH) extraction.


One additional test condition parameter is used to help minimize the ringing caused by the parasitics in the system.


What external gate resistor (RG) is used?

RG is used to slow the gate drive signal and therefore, minimize the 2nd order ringing caused primarily by LPL and the output capacitance (COSS). The higher the RG, the slower the turn-on and turnoff events and therefore, less ringing. However, the consequence is slower switching times and larger energy loss. This makes the switching characteristics in the data sheet appear worse. So, you often see many different RG values specified as device manufacturers find the optimized situation where the ringing still allows repeatable parameter extractions, without slowing down the turn-on and turn-off of the device too much. In addition to RG, the gate drive ICs and supporting circuit, also impact the turn-on and turn-off times.


Switching parameter extraction method.

Figure 5: Switching parameter extraction method.


The other necessary step to determine the dynamic characteristics is to extract the desired parameters from the waveforms on the oscilloscope. Again, there are more than one way to extract parameters from the waveforms and data sheets will often diagram the method used (e.g. Figure 5) or reference a standard (e.g. IEC 60747-8). Even then, there is still interpretation left to the test engineer. Because of ringing, it is possible to have multiple crossings of an extraction threshold (Figure 6). So, how would you interpret tr in Figure 6? The definition for tr is 90% VDS → 10% VDS. However, that could be ~ 41 ns if you use the first crossing of the 90% threshold (shown with top horizontal orange marker) or ~23 ns if you use the third crossing of the 90% threshold. The standard definitions for parameter extractions, don’t always lead to consistent results when real waveforms have ringing and render the standard extraction ambiguous. New standards need to be developed, considering the inevitable ringing in the switching waveforms, so parameters extractions can be more consistent.


Turn on event (VDS – red, ID – green, VGS – blue).
Figure 6: Turn on event (VDS – red, ID – green, VGS – blue).


Reverse Recovery Characteristics

Now let’s investigate reverse recovery characteristics. Figure 7 shows a typical section from a 1200V SiC MOSFET data sheet describing some reverse recovery specifications.


Data Sheet Reverse Recovery Characteristics. (source: page 2, C3M0021120D Datasheet – Rev. -, 08-2019)
Figure 7: Data Sheet Reverse Recovery Characteristics. (source: page 2, C3M0021120D Datasheet – Rev. -, 08-2019)


Reverse Recovery Time (trr), Reverse Recovery Charge (Qrr), and Peak Reverse Recovery Current (Irrm) are the most common parameters specified in data sheets. In many DPT setups, the load inductor (L) is connected to the ground reference and the body diode in the DUT (low side device) is tested. The low side device is turned off, and the high side device is pulsed to energize L with the specified current. Some data sheets show the test setup, but others leave it to your decision and just provide test conditions.

There are common operating conditions specified for reverse recovery characteristics, similar to what is specified for switching characteristics:

  • VDD/VDS = 800V
  • ID = 50A
  • Temperature = 175˚C


However, VGS has a different meaning in reverse recovery. In the example in Figure 7, the VGS = -4V refers to turning off the DUT with the body diode that is getting tested. Note (1) specifies the maximum values (VGSmax = -4v/+19V) for driving the ‘high side’ MOSFET in the DPT configuration. The ‘high side’ MOSFET drives the double pulses to test the reverse recovery of the DUT (MOSFET that is turned off). The reason only a maximum is given will become evident shortly.

The final test condition is the dif/dt (1000 A/µs), which requires us to look at how the waveform is extracted to interpret what is meant. There are multiple standards in the industry which define the reverse recovery parameter extractions, so it is important to understand which is being used. And as mentioned above, data sheets will often provide a diagram to show how they are extracting the parameters (Figure 8).


Reverse Recovery Extraction Method. (source: Figure C., IMW120R045M1 Datasheet – Rev. 2.5 2020-06-12)
Figure 8: Reverse Recovery Extraction Method. (source: Figure C., IMW120R045M1 Datasheet – Rev. 2.5 2020-06-12)


IF is the forward current flowing through the body diode (reverse polarity for the MOSFET) that is generated when the body diode is freewheeling the current between the two pulses. When the second pulse starts, the current flows through the other MOSFET, ‘turning -off’ the current in the body diode, enabling the reverse recovery to be measured. The current descends toward 0 A at a rate of diF/dt. As the current becomes negative, the reverse recovery phenomenon starts as shown in Figure 8. One might think diF/dt is an input you can specify in your test system, because it is specified in the test conditions. However, diF/dt is controlled by two other test conditions you control:

  • The external gate resistor (Rg) used to drive the MOSFET.
  • The gate to source voltage (VGS) that is used to drive the high-side MOSFET. Now the meaning of Note 1 becomes clear.


So, the process of measuring reverse recovery parameters is iterative. One must choose a value for Rg and VGS and run a DPT to see what diF/dt is achieved. If the value is lower than the required test condition, then Rg can be reduced to speed up the response, or VGS can be increased to speed up the response. Then a second DPT is run to see how the changes in Rg or VGS affected the resultant diF/dt. This process iterates until a the desired diF/dt is achieved. In practice, one typically uses Rg as a coarse adjustment for diF/dt, until the slope is close to the desired value. Then it is easier to change VGS as the fine control to tune diF/dt to the desired value.

Finally, the extraction of diF/dt can be done in different ways. One standard specifies that it should be calculated from 50% of IF to 75% of Irrm. While other extractions will differentiate the current across the declining slope of IF/Ir and take the maximum of this differentiated value as diF/dt. Therefore, care must be taken in extracting the appropriate diF/dt to expect correlation with data sheet values.



Interpreting and validating dynamic characteristics of power semiconductors in data sheets is not easy. As we have discussed, there are many aspects of the measurement setup, that are not included in the test conditions that significantly impact the results. As well as, approaches to extracting the parameters from the switching and reverse recovery waveforms. To help create standards for WBG devices, the JEDEC JC-70 standards was initiated in September of 2017 to develop industry standard tests for GaN and SiC. For each subcommittee, there are task groups focused on ‘Reliability and Qualification Procedures’, ‘Datasheet Elements and Parameters’, and ‘Test and Characterization Methods’. Keysight is a contributing member to the JC-70 standard for both GaN and SiC subgroups.

Keysight designed the PD1500A Dynamic Power Device Analyzer as a complementary dynamic characterization solution to the B1505A/ B1506A Power Device Analyzers you have learned to count on. We focused on providing repeatable and reliable dynamic DPT measurements for discrete Si/SiC based power semiconductors. We are continuing our R&D investment in state-of-the-art measurement techniques for DPT solutions. Recently we introduced a customized GaN FET Test board, that works with the standard PD1500A system (see October’s edition of Bodo Power Systems). The PD1500A test methods are following the standards being create by the JC-70 standard. To learn more about Keysight’s PD1500A Dynamic Power Device Analyzer, please visit the website ( PD1500A). Look for future articles from Keysight, with more discussion regarding repeatable and reliable Double-Pulse Test results.


About the Authors

Ryo Takeda works as a Solution Architect at Keysight Technologies Incorporated, a company driven to deliver breakthrough solutions and trusted insight in electronic design, test, manufacture, and optimization to help customers accelerate the innovations that connect and secure the world.

Michael Zimmermann is an R&D Engineer at Keysight Technologies Deutschland GmbH.

Mike Hawes is the automotive and energy solutions planning manager at Keysight Technologies. Hawes holds a Master's Degree in Biomedical Engineering from Colorado State University. He also holds a Bachelor's Degree in Electrical Engineering from Washington State University.


This article originally appeared in the Bodo’s Power Systems magazine.