Technical Article

Inevitability of Near Chip-Scale SMD Packaging for Power GaN and SiC

July 25, 2018 by Courtney Furnival

This article is a Q&A aiming to provide insight into the benefits of WBG near chip-scale package capability and its ultimate form, the μMaxPak package technology.

Today’s performance of power Wide Band-Gap (WBG) devices is severely limited by conventional power packages (i.e., TO220, TO247, and IGBT DBC-modules). We are seeing some early power QFN and LGA WBG packages with modest improvements, but they are still performance-limiting and costly. Future higher performance power WBG evolution will simply not be possible without near chip-scale SMD packages. Such near chip-scale SMD packages are absolutely required for power WBG device’s potential power density, performance, speed, efficiency, and costs. 

There is a symbiotic relationship between power WBG devices and near chip-scale SMD packages, or more specifically these packages enable power WBG and power WBG enable near chip-scale packages. The inevitability of near chip-scale power WBG packaging can be better understood by looking at the example of today’s digital microprocessor’s integration and packaging. In principle, hundreds of thousands of transistors could be packaged as discretes and soldered together, but such a maze of leads and interconnects would have unacceptable parasitics, size, reliability, and cost. Discrete microprocessors would just not be possible. Going one step further, the proprietary μMaxPak package architecture is an optimum example of ideal near chip-scale packaging.

The following frequently asked questions provide insight into the benefits of WBG near chip-scale package capability and its ultimate form, the μMaxPak package technology.


Q: Are near-chip-scale SMD packages really inevitable for power WBG devices?

A: Yes they are inevitable. Near-chip-scale SMD packages are small, Ieadless, and wire bondless, approaching the size of the chips enclosed. They are essential for the full performance of power WBG devices because they reduce parasitics and thermal resistance (Rjc) thereby improving WBG speed, efficiency, reliability, and cost while allowing similar improvements to the overall system. The μMaxPak is an example of Ultimate Near Chip-Scale WBG packaging.


Q: What are the primary performance advantages of the μMaxPak packages?

A: The μMaxPak is the ultimate implementation of the Near Chip- Scale packaging concept because it minimizes parasitics and maximizes heat transfer. This is accomplished by minimizing current loop path length with leadless and wire bondless packages, thus enabling power WBG devices to operate at maximum efficiency by reducing both conduction and switching losses. Furthermore, the exceptionally low package thermal resistance Rjc enhances reliability and increases the maximum current rating. Table 1 quantifies potential performance advantages for μMaxPak half-bridges with WBG die size between 5mm x 5mm and 7mm x 8mm.


Primary QFN-μMaxPak Performance Advantages.


Q: If more efficient WBG devices reduce power dissipation, why is lower package thermal resistance required?

A: Although higher WBG efficiencies are reducing power dissipation significantly, the WBG die power densities are increasing about twice as fast as efficiencies. Therefore, thermal resistance per unit area must be reduced. The basic μMaxPak packages utilize robust Cu conductors and reduced solder interfaces to more effectively remove heat from both the top and bottom of the die. For very high power dissipation products, more heat can be removed with heatsinks or coldplates on both the top and bottom of the package. Looking to the future, potentially GaN and SiC operating temperatures will increase, further enhancing heat dissipation.


Q: Why have chip-scale SMD packages not been used for power Si IGBT modules?

A: Si IGBT modules require very large IGBT and diode die. Such large die cannot be soldered directly to Cu leadframes, because of large coefficient of thermal expansion (CTE) mismatch between Cu and die. This is acceptable for smaller die where we see smaller discrete IGBT and diode die soldered directly to Cu leadframes or to the bases of TO220 and TO247 packages, but the much larger IGBT die in modules require a DBC CTE buffer between die and base plate.


Q: Why can higher current SiC and GaN die be used directly on Cu?

A: Power SiC and GaN die can have 10 times the current density of Si IGBT die, which enables die to be 1/10th the size. Therefore, WBG devices in Near Chip-Scale SMD packages can be soldered to Cu leadframes and operate at hundreds of amperes.


Q: What are the basic types or structures of μMaxPak architecture?

A: The μMaxPaks are molded, leadless, and wire-bondless SMD packages, like the QFN and LGA packages. They can uniquely accommodate double-sided assembly of the internal leadframe or substrate. The double-sided assembly is made possible by the proprietary bottom-side cavity (or cavities) architecture.

Standard Type 1 QFN-μMaxPak packages have the power die soldered into the bottom cavity(s) of the QFN leadframe (or LGA substrate) with the die gate (G) and source (S) pads soldered to the leadframe, leaving the die drain (D) pad(s) exposed at the bottom of the package. The Type 1 configuration is Ideal for vertical integration with additional components on the top of the leadframe (or substrate). These components can include bump-chip gate-drivers (GD), isolators and passive components. The cross-section in Figure 1 is a Type 1 example with a vertical WBG die in the bottom cavity and GD IC on top of the leadframe.


Type 1 example with a vertical WBG die in the bottom cavity and GD IC on top of the leadframe.
Figure 1. Type 1 example with a vertical WBG die in the bottom cavity and GD IC on top of the leadframe.


Inverted Type 2 QFN-μMaxPak packages have the power die soldered into the cavity(s) in the bottom of the leadframe (or substrate), but with the D pad(s) soldered to the leadframe and the G and S pads exposed at the bottom of the package. The Inverted Type 2 μMaxPak allows horizontally integrated gate-drivers, which can be external or internal (Horizontal gate-driver options not shown). See cross-section in Figure 2.


Inverted Type 2 μMaxPak allows horizontally integrated gate-drivers
Figure 2. Inverted Type 2 μMaxPak allows horizontally integrated gate-drivers.


Thin Type 3 QFN-μMaxPak packages are Inverter Type 2 μMaxPak with the leadframe also exposed at the top of the package. They are robust, and accommodate both top and bottom heatsinks. They are well suited for EV Inverters, which are usually clamped between top and bottom cold plates. See cross-section in Figure 3.


QFN-μMaxPak packages are Inverter Type 2 mMaxPak
Figure 3. QFN-μMaxPak packages are Inverter Type 2 mMaxPak


Q: Why use modified QFN μMaxPak packages for power WBG packaging?

A: The QFN structure is simple, robust, reliable, and low cost. The mature commercial QFN/DFN package technology is flexible and available at many contract assemblers. Its flexibility allows easy size and layout customization without hard tooling, allowing packages to be optimized for each product configuration, optimizing performance and reducing tooling NRE, design/process risk, and new product time-to-market. These advantages are built on inherent features like being leadless and wire bondless, with a heavy single piece of Cu leadframe that provides connections from the top of the die to the bottom-side pads. These features contribute to the exceptionally low inductance, electrical resistance, and thermal resistance.


Q: Why are chip-scale μMaxPak QFN packages so cost-effective?

A: The QFN packages are small, and they have simple internal structures to the one-piece leadframe. They do not require internal DBC for CTE buffer, and they do not require complex external leads and terminals. Existing Power QFN packages often replace wire bonds with solder clips, increasing assembly complexity, NRE, interfaces, cost, size and reliability risks. The proprietary μMaxPak architecture eliminates solder clips and easily accommodates multi-chip configurations like half-bridge (HB), full-bridge (FB) and 3-phase bridge (3P).


Q: What are the differences between a leadframe-based and a substrate-based μMaxPak?

A: Leadframe and substrate μMaxPak use the same proprietary architecture having die cavities(s) on the bottom of the package and components or supplementary heatsink/cold-plate on the top. Although QFN are LGA packages, and LGA can be QFN packages, it is common to call Leadframe μMaxPak packages “QFN” and Substrate μMaxPak packages “LGA.”


Q: What are the pros and cons of QFN versus LGA μMaxPaks?

A: Leadframe-based QFN μMaxPaks utilize thicker and wider Cu interconnects, creating an optimum 3-D geometry. This provides the lowest current-loop-inductance, lowest current-loop electrical resistance, and is mechanically more robust. It also provides the lowest thermal resistance (Rjc), and highest heat capacity to better accommodate repetitive peak power pulses.

The simple one-piece leadframe assembly provides lower costs than the LGA-μMaxPak. Substrate-based LGA μMaxPaks also have low current loop inductance and low electrical resistance, but not as low as the QFN μMaxPak. Their substrates are PCBs or laminates and use high-temperature laminate materials with Cu foil and Cu via for electrical and thermal connections. Since Cu foil and via are not as heavy as solid Cu leadframes, electrical and thermal internal connection of the LGA μMaxPaks can never perform quite as well as QFN μMaxPaks.

That said, since both QFN and LGA μMaxPak packages have exposed die pads on the bottom of the package as primary heat dissipation path, the thermal resistance Rjc of the LGA μMaxPak is still nearly as good. LGA substrates can provide thinner traces and more complex interconnects, which allows more complex circuitry and vertical integration. Circuit density can be further increased in LGA μMaxPak by embedding passive component in the laminate substrate.


Comparison, QFN-μMaxPak versus LGA-mMaxPak.


Q: Can μMaxPak architecture accommodate both lateral and vertical WBG die?

A: Yes it can. The vertical die structure is most common for power SiC, and ideal for near chip-scale packaging, because all power pads provide both electrical and thermal external connections, and they provide the best high-voltage separations with D pads on one side and S/G pads on the other. Power GaN die are typically lateral structures with all electrical connections on the top-side of the die, while the other side contains only thermal pads. With G, S, and D on the same side, the pads are smaller and the high voltage spacing (S to D) must be large, which can limit maximum current and voltage. An exception is GaN-on-SiC die, which can accommodate thru-SiC via to bring the D to the other side. GaN-on-SiC is more expensive today, but better thermally.


Q: Can μMaxPak accommodate both normally-off and normally-on WBG die?

A: Yes it can, but normally-on die does increase the package's complexity. Normally-on die are typically managed with a cascoded circuit, which requires a low-voltage MOSFET die in series with the high-voltage WBG die, and extra internal connection(s). Normally-off die are easiest to manage. Today most power WBG die are normally-off. However, cascoded switches still have advantages in some applications. 


Q: How are signal pads and connections managed in μMaxPak?

A: WBG power and signal die pads vary by manufacturer, ratings and, product. Therefore, it is recommended that the die pads and μMaxPak pads be co-designed for performance, manufacturability, and reliability. Ideally, all connections will be soldered to the QFN leadframe pads or LGA foil pads. Signal pads often include gate, sense, and current sense pads. External signal pads will be different with integrated gate driver(s).


Q: Can μMaxPak packages accommodate multiple WBG power die?

A: Yes it can. The μMaxPak architecture can accommodate single or multiple WBG switches, and each switch can accommodate paralleled WBG die and anti-parallel diodes. Common configurations for multiple switch μMaxPak can be HB, FB, and 3P, and they can be easily customized for special configurations. FB and 3P are best suited for lower power levels, and at higher power levels it can be more practical to create them with multiple HB packages. In general, the half-bridge provides higher power density and lower current-loop inductance than two single-switches.

An example of a SiC μMaxPak HB is shown in Figure 4A (Cross-Section) and Figure 4B (Bottom-side pads).


HB cross-section view (top); HB bottom pad view (bottom)
Figure 4. HB cross-section view (top); HB bottom pad view (bottom)


This HB structure has a non-inverted high-side power die and an inverted low-side power die enabling it to be directly soldered on the positive and negative bus to minimize loop-inductance.


Q: Are μMaxPak packages suitable for higher WBG operating temperatures?

A: GaN can operate at higher temperatures than Si, and SiC at higher temperatures than GaN. Today‘s power GaN and SiC devices are usually not operated above 150°C, being primarily limited by increased Rds(on) at higher junction temperatures, but both WBG materials can accommodate much higher operating temperatures as WBG devices evolve. The μMaxPak package operating temperature can be limited by the choice of solder and molding compound, and by CTE mismatch. LGA μMaxPak packages can additionally be limited by choice of substrate laminate material.

Today’s typical QFN and LGA materials can accommodate temperatures Tj(max) of 185°C, with typical Sn/Ag/Cu solders, Hi-Tg molding compounds, and laminates like BT resins. There are higher temperature materials available today, which can allow μMaxPak Tj(max) up to about 225°C in the μMaxPak packages


Q: Is it true that μMaxPak technology improves system architecture and performance?

A: Yes it does. The small and thin packages significantly reduce system size and weight. Smaller power SMD packages can be placed close together eliminating heavy leads, bulky terminals, and large spacing/creepage distances, reducing integrated system size, weight, and cost. The total current loop-inductance and resistance of integrated system interconnects are typically larger than that of the packages.

The μMaxPak packages virtually eliminate most high current/ voltage internal connectors and interfaces. Furthermore, tighter control, feedback, and protection circuitry are more easily implemented.


Q: Are UL/EN isolation and safety regulations met by near chip-scale packages?

A: Yes, the smaller UL minimum spacing and creepage distances are already used inside traditional power Si IGBT modules, where die, traces, and passive chips are small and thin, allowing easier coating or potting. Likewise, the small and thin μMaxPak packages make coating, potting and under-fill much easier, especially in enclosed integrated systems. Under-fill, coating, and potting materials must be suitable for pollution degree 1 minimum spaces and creepage distances, like those used inside traditional high power Si IGBT modules.


In Summary: WBG Devices Need SMD Packages

Power WBG (GaN and SiC) devices need near-chip-scale SMD packages to reach today’s WBG devices full performance, efficiency, and power density potential. Inevitably such packages will be absolutely required as power WBG devices evolve toward the inherent potential of GaN and SiC materials. Increased WBG power density and efficiency has enabled new packages like the μMaxPak, and the μMaxPak packages enable the power WGB full performance, efficiency and power density.

Furthermore, near chip-scale μMaxPak packages reduce unit cost, tooling NRE, and new product time-to-market. These packages are compatible with standard QFN and LGA assembly technologies, which are reliable, robust, and available today. Small SMD packages can also simplify system structures increasing system performance, efficiency, and power density, while reducing system cost.


About the Author

Courtney Furnival is the president of Semiconductor Packaging Solutions since October 2018. 


This article originally appeared in the Bodo’s Power Systems magazine.