Tech Insights

International Electron Devices Meeting 2018 Reflections and Review

February 08, 2019 by Gary Dolny

The annual IEDM conference, held December 1-5, 2018 in San Francisco, CA, USA, is sponsored by the IEEE Electron Devices Society. It is the world’s largest

The annual IEDM conference, held December 1-5, 2018 in San Francisco, CA, USA, is sponsored by the IEEE Electron Devices Society. It is the world’s largest and most influential forum for reporting technological breakthroughs in all areas of semiconductor and electron-device technology, design, manufacturing, physics, and modeling.


This year’s IEDM was attended by over 1700 scientists and engineers from around the world representing all areas of micro and nanoelectronics. The conference technical program consisted of 232 presentations including both invited and contributed papers, as well as an opening plenary session, an evening panel discussion, and four special focus sessions.


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The contributed papers were stringently reviewed with an acceptance ratio of 35% to ensure the highest quality presentations. “This year’s program shined the spotlight on technology advances that are driving the electronics industry forward, such as neuromorphic and 3D integration; device concepts for 3nm; progress in many types of advanced memories; new high-mobility channel materials, interconnect strategies; and many others,” said Kirsten Moselund, IEDM 2018 Publicity Chair and Research Staff Member at IBM Research– Zurich. “Also, this year the IEDM once again featured special sessions of invited papers focused on some of today’s most important areas of research. This year’s Focus Session topics were quantum computing, 5G wireless communications, wide-bandgap power devices, and the future of interconnects.”

“Apart from the technical program itself, the 2018 IEDM offered many other opportunities to gain insight into new technologies, to interact with technology leaders, and to take part in stimulating discussions,” said Rihito Kuroda, IEDM 2018 Publicity Vice Chair and Associate Professor at Tohoku University. “The weekend tutorials and Short Courses, for example, provided outstanding opportunities to learn what is happening at the frontiers of many different technologies. The Tuesday evening panel offered the chance to debate the future of electronics technology with key technologists, while a new luncheon format earlier that day provided the opportunity to hear industry leaders give their personal career reflections. Also, a supplier exhibition was held once again to showcase products and services which support the industry.”


Special Focus Session: Power Semiconductors

This year’s IEDM reflected a renewed emphasis on power semiconductors, particularly on wide-bandgap devices and technology. Two full contributed sessions, as well as a special focus session, were directed to power devices in SiC, GaN and other related materials. In addition, the conference featured a 90-minute tutorial on the topic of “Power Transistors in Integrated BCD Technologies”.

The first of the power device sessions addressed advances in silicon carbide, gallium nitride, and silicon power devices. Two papers from the National Institute of Advanced Industrial Science and Technology, (AIST) Ibaraki, Japan presented performance breakthroughs in silicon carbide superjunction MOSFETs. The first, titled, “0.63 mΩcm2/ 1170 V 4H-SiC Super Junction V-Grove Trench MOSFET,” [1] claimed the lowest specific on-resistance ever reported in a SiC power transistor with a blocking voltage ≥600 V. The measurements were made on a device mounted in a 5-pin TO-268 having a Kelvin source terminal.

The excellent electrical properties were realized with the structural combination of a V-groove MOS channel and the charge balance in the superjunction drift region. The superjunction structure was formed through a 6-step n-type epitaxial growth process with Al implants to form the p-type pillar regions. The cell pitch was 2.5 μm with p-pillar widths ranging from 1.0-1.5 μm. The gate regions were formed using a wet chemical process to orient the MOSFET channels along a {08} crystal plane to maintain high inversion layer mobility. The substrate was also thinned to 50 μm.

A second presentation by AIST characterized the dynamic performance of the superjunction SiC MOSFET including turn-on, turn-off, and short circuit characteristics [2]. The turn-on and turn-off characteristics with an anti-parallel Schottky barrier diode exhibited no degradation from the SJ structure, in spite of its large drain-source capacitance. The short-circuit withstand time of 7.2 μs was comparable to that for a non-SJ UMOSFET. A team from Mitsubishi Electric Corporation and University of Tokyo discussed channel engineering of 4H-SiC MOSFETs using sulfur as a deep level donor [3].

The sulfur-doped channel was shown to provide 31% reduction of specific on-resistance (Ron) at higher threshold voltage (Vth=4V) compared with channels doped by conventional shallow level donors. The effect of S atoms in the channel region is believed to depend on its charged state. Neutral S atoms increase Vth by trapping electrons at its impurity level. Ionized S atoms reduce the electric field at the MOS interface which leads to an increase in the inversion layer mobility.

Additionally, the Vth shift under positive or negative bias stress of Vg tended to be reduced in samples with S doping. Finally, S doping in the channel was also shown to reduce the temperature dependence of channel resistance. A team from Cornell University, Kyoto University, and Novel Crystal Technology, Inc. presented vertical trench Schottky barrier Ga2O3 diodes (SBD) with 2.44 kV breakdown and low reverse leakage current [4]. The experimental devices were formed on bulk Ga2O3 substrates with a 10 mm thick halide vapor phase epitaxial layer. The SBD region is based on a trench-type metal-insulator-semiconductor structure which takes advantage of the reduced surface field (RESURF) effect. The mesa widths were in range of 1-4 μm and the trench depth was 1.55 μm. The trench corners were intentionally rounded using a wet/ dry etching process to reduce electric field crowding. They demonstrated a breakdown voltage of 2.44 kV and BV2/Ron figure of merit of 0.39 GW/cm2.


Special Focus Session: Challenges for Wide Bandgap Device Adoption in Power Electronics

A special focus session titled Challenges for Wide Bandgap Device Adoption in Power Electronics featured a team of experts who interpreted the current status of both GaN and SiC technology and discussed challenges to the widespread adoption of these technologies. The presentations included:

  • SiC Devices for Mainstream Adoption, Peter Friedrichs, Infineon
  • The Current Status and Future Prospects of SiC High Voltage Technology, Andrei Mihaila, ABB
  • Progress in High and Ultra-High Voltage Silicon Carbide Device Technology, Yoshiyuki Yonezawa, AIST
  • Effects of Basal Plane Dislocations on SiC Power Device Reliability, Robert E. Stahlbush, Naval Research Laboratory
  • GaN Devices for Automotive Applications and Their Challenges in Adoption, Tetsu Kachi, Nagoya University
  • Barriers to the Adoption of Wide Bandgap Semiconductors for Power Electronics, Isik Kizilyalli, ARPA-E
  • GaN Power Commercialization with Highest Quality-Highest Reliability 650V HEMTs- Requirements, Successes and Challenges, Primit Parikh, Transphorm

The general conclusions drawn were that the wide-bandgap device technologies offer potentially huge savings in energy usage and improved efficiency compared to existing solutions. However, to ensure the adoption of these technologies, innovation is required at all levels of the supply chain including material quality and availability, device fabrication, system design, circuit architecture, qualification metrics, and market and business models. It was also emphasized that wide bandgap devices cannot be considered as drop-in replacements in existing Si-based systems. Systems must be re-designed to take full advantage of the wide-bandgap devices and their enhanced capabilities. Reliability and cost also remain important considerations.


Special Focus Session: Advances in GaN Power Devices

The third session was devoted to advances in GaN power devices. A group from Toyota R&D Labs, Kyoto University, and Nagoya University described a homoepitaxial GaN p-n diode with a near-ideal critical breakdown field of 2.8-3.5 MV/cm. [5] The device was a mesa-type structure with a beveled edge termination. The bevel angle was kept shallow <15° and a double-sided-depletion design was used. This allowed the depletion layer to spread into both p- and n-type material. TCAD simulations showed that field-crowding does not occur, and a uniform bulk breakdown was verified using luminescence measurements.

A team from the University of Padova and Cornell University presented a fundamental study of avalanche breakdown in polarization- doped vertical GaN p-n diodes [6]. They experimentally demonstrated that high-voltage GaN-based devices with polarization doping exhibit avalanche breakdown but also a time-dependent recoverable walk-out mechanism. They used temperature-dependent DLTS measurements to show that the existence of the walkout mechanism is caused by hole emission from residual carbon. The authors emphasized that this phenomenon has not been previously reported for GaN and its improved understanding is necessary for the design of reliable high-performance GaN devices.



Two presentations were devoted to GaN HEMT reliability and performance degradation issues. A group from the Hong Kong University of Science and Technology addressed HTRB reliability in E-mode GaN MIS-HEMTS due to hole degradation. [7] Under high gate-to-drain reverse bias holes tend to drift through the gate dielectric, leading to the generation of defects. This can lead to non-recoverable Vth shifts and catastrophic breakdown during time-dependent dielectric breakdown (TDDB) stress. They showed that these effects can be effectively suppressed by replacing the conventional GaN channel with a GaOxN1-x channel. The GaOxN1-x layer is formed after gate-recess etching by exposing the etched GaN layer to an oxygen plasma in an ICP chamber followed by in-situ annealing in NH3.

A team from the University of Padova and Infineon addressed both TDDB degradation as well as hot-electron effects in GaN HEMTS [8]. The presentation reviewed three important aspects of GaN HEMT degradation. The first was the impact of substrate and buffer properties on the breakdown voltage characteristics of the devices. The second was the mechanism of time-dependent breakdown of the semi-insulating GaN buffer which can lead to a premature failure of the devices. Finally, the degradation of the dynamic properties of the transistors under hard switching conditions was reported.

The results presented indicated that through proper optimization of device properties it is possible to fabricate transistors with excellent dynamic performance and reliability.


IEDM 2019 

IEDM 2019 will be held from December 9-11, 2019 at the San Francisco Hilton Union Square. Additional information is available through IEEE



  1. T. Masuda, et. al., “0.63 mWcm2 / 1170 V 4H-SiC super junction v-groove trench MOSFET”, IEDM Technical Digest, Dec. 2018, pp. 177-180.
  2. S. Harada, et. al., “First demonstration of dynamic characteristics for SiC superjunction MOSFET realized using multi-epitaxial growth method”, IEDM Technical Digest, Dec. 2018, pp. 181-184.
  3. M. Noguchi, et. al., “Channel engineering of 4H-SiC MOSFETs using sulfur as a deep level donor”, IEDM Technical Digest, Dec. 2018, pp. 185-188.
  4. W. Li, et. al., “2.44 kV Ga2O3 vertical trench Schottky barrier diodes with very low reverse leakage current”, IEDM Technical Digest, Dec. 2018, pp. 193-196.
  5. T. Maeda, et. al., “Parallel-plane breakdown fields of 2.8-3.5 MV/ cm in GaN-on-GaN p-n junction diodes with double-side-depleted shallow bevel termination”, IEDM Technical Digest, Dec. 2018, pp. 687-690.
  6. C. De Santi, et. al., “Demonstration of avalanche capability in polarization-doped vertical GaN pn diodes: study of walkout due to residual carbon concentration”, IEDM Technical Digest, Dec. 2018, pp. 691-694.
  7. M. Hua, et. al., “Suppressed hole-induced degradation in E-mode GaN MIS-FETs with crystalline GaOxN1-x channel”, IEDM Technical Digest, Dec. 2018, pp. 695-698.
  8. M. Meneghini, et. al., “Power GaN HEMT degradation: from time-dependent breakdown to hot-electron effects”, IEDM Technical Digest, Dec. 2018, pp. 703-706.