SiC Cascodes and Their Advantages in Power Electronic Applications


Christopher Rocneanu, Director Sales Europe & North America at United Silicon Carbide Inc.

Silicon carbide cascodes are hybrid devices that give the advantages of a wide band-gap semiconductor switch with the flexibility and ruggedness of silicon MOSFETs. They can be used as drop-in replacements in legacy systems as well as next-generation power converters and inverters.

 

Wide Band-gap Devices Make Attractive Promises ...

It’s hardly necessary to describe the qualities of wide band-gap (WBG) devices using silicon carbide (SiC) and gallium nitride (GaN) technology. The headlines promise extreme power densities and matching efficiencies, with examples such as the recent “Little Box Challenge” that saw the target power density for a specified converter beaten by a factor of three. In real systems, designers want normally OFF switches – which SiC MOSFETs and enhancement-mode GaN (e-GaN) HEMT cells provide – but they are not perfect; each has its own limitations and quirks.


Both types need very specific gate-drive voltages; SiC MOSFETs have relatively poor body diodes and GaN devices have no classical body diode and no avalanche voltage characteristic. In many practical applications, a body diode or equivalent is needed, for example in “choppers,” half-bridges and “totem-pole” PFC stages. For sensible efficiencies, SiC-MOSFETs and GaN HEMTs need a parallel high-performance diode, adding to the overall cost and complexity.

 

SiC Cascodes: A Modern Twist on an Old Idea

To try to make the best of WBG technology, manufacturers have revisited an old idea from the 1930s, where vacuum tubes were put in series to form a hybrid device with performance better than either of the individual parts. The technique was christened “cascode” and has resurfaced over the years in BJT and MOSFET form.

In its WBG implementation, a cascode is a series connection of a Si-MOSFET and a normally ON SiC-JFET (Figure 1). When the gate is high, the MOSFET is ON, shorting the JFET gate-to-source, forcing it ON. When the MOSFET gate is low, its drain voltage rises until the JFET gate-to-source voltage reaches about -7V, turning it OFF and leaving about 7–10V on the MOSFET drain.

The hybrid becomes normally OFF, the gate-drive voltages are now non-critical and the body diode of the MOSFET is fast with very low reverse recovery charge and has low voltage drop. These attributes stem from the fact that the MOSFET is a low-voltage type, optimized for the application and typically co-packaged with the SiC die.

 

Figure 1: Cascode arrangement of Si-MOSFET and SiC-JFET
Figure 1: Cascode arrangement of Si-MOSFET and SiC-JFET

 

The cascode can now stand as a compelling alternative to SiC-MOSFETs, GaN HEMTs and are readily used in legacy designs that currently use Si-MOSFETs and IGBTs. Comparing a typical 650V cascode with other WBG devices and a super junction Si-MOSFET, Table 2 gives some headlines.

 

Table 2: SiC cascodes compared with other WBG devices and super junction

Technology SiC Cascode650V – 45mΩ(UJC6505K) CommercialSiC MOS-FET Gen 3 CommercialE-GaN HEMT Commercial Si-Super-junction MOSFET
RDSA 0.75 mΩ-cm2 2-3 mΩ-cm2 3-7 mΩ-cm2 10 mΩ-cm2
Normalized Die Area 1 2.6x 4x  
EOSS 7.5 μJ 22 μJ 12 μJ 14 μJ
RDS*EOSS 255 660 350 480
VTH 5 2.8 1.3 3.5
Avalanche Capability YES YES NO YES
Short Circuit YES YES NO YES
Gate Drive maximum +/-25V +22/-6V +7/-10V +/-20V
Gate Drive Recom-mended +12/0V +18/-0V +6/-3V +12/-5V
Intrinsic diode Qrr 85nC 53nC No diode 13μC
Intrinsic diode Vf 1.5V 4.3V No diode 0.9V

 

 

MOSFETs

A stand-out value is the figure of merit RDSA, implying a very small die size, all else being equal. This, in turn, gives low “Miller” input and output capacitance COSS, leading to low switching-loss EOSS, and a class-leading figure of merit for overall losses, RDS*EOSS. Cascodes perform well under avalanche conditions with a natural clamping effect, unlike GaN for example, which has no avalanche rating. Momentary short-circuits of 4μs or more are handled well by cascodes with high saturation currents, “pinching off” the channel.

 

Positive Temperature Coefficient (PTC)

The PTC of ON-resistance also helps. Unlike the other devices, the saturation current is not dependent on the gate-drive voltage and remains near-constant after full enhancement at about 8V VGS.

 

Thermal Conductivity

Although die size is small, heat transfer is still efficient, with SiC having thermal conductivity three times better than GaN or Si and a high TJ(MAX), typical of a WBG device.

The wide +/-25V gate-drive voltage swing allowed with cascodes means that systems designed for Si or SiC MOSFETs are directly compatible, so cascodes can be drop-in replacements in this respect. Even IGBT gate-drive swings of typically +15/-9V will drive the cascodes happily, offering the prospect of changing out the old switch technology for better performance, or as older devices become obsolete.

 

Battery Charger Manufacturer

A case study with a battery charger manufacturer, changing out IGBTs for cascodes, resulted in 1.5% efficiency savings and 30% more power throughput at the 10kW level [1]. Cascode gate charge is significantly less than IGBTs and, if the gate-voltage swing is adjusted to be lower, gate-drive power requirements are cut dramatically. Cascodes are available in the familiar TO-247 format so will often mechanically drop into IGBT or Si/SiC-MOSFET sockets, but minor changes to the gate-drive circuit will optimize the solution.

 

Typical SiC Cascode

Figure 3 shows a typical circuit with separate values for R(ON) and R(OFF), which gives effective control of dV/dt and di/dt levels. The ferrite bead damps oscillations as necessary depending on layout. A negative gate-drive voltage is not necessary to prevent injection of current into the gate from drain dV/dt causing spurious turn-ON, as the Miller capacitance is effectively absent. Layout around the gate should anyway follow good practice as shown, as with any switch type, to minimize inductance in the source connection, which might couple voltage transients into the gate from channel di/dt.

 

Figure 3: Typical SiC cascode gate drive
Figure 3: Typical SiC cascode gate drive

 

 

The comparison table also shows that the intrinsic diode recovery charge of SiC cascodes compares favorably and, combined with its low forward drop Vf, gives minimum energy loss in circuits where the diode conducts. Figure 4 shows comparative waveforms with a cascode and SiC MOSFET, with and without external diode, with an 800V inductive load at 150°C. Using the double-pulse method, as the cascode turns OFF, it clearly shows shorter recovery time and lowers dissipated energy.

There is literally no direct comparison with GaN, as the technology has no intrinsic diode, but GaN will conduct in reverse as the channel conductivity increases when the drain gate voltage goes negative. There is no reverse recovery charge, but the voltage drop is relatively high so a parallel diode is usually added when reverse conduction is required, adding in its own recovery characteristics.

 

 

Figure 4: Cascode intrinsic diode reverse recovery characteristics

Figure 4: Cascode intrinsic diode reverse recovery characteristics

 

 

The applications

As well as being replacements for IGBTs and Si-MOSFETs in legacy systems, cascodes with their near-ideal combination of specifications and small die size are contenders for new designs in the key areas of motor drives, inverters, PVs, welding, class D audio amplifiers, EVs/HEVs and more. With a “ground-up” approach to design, the high-frequency capability of the devices can be exploited to leverage gains in magnetics and passive component sizes.

Major benefits are seen particularly in the bridgeless totem-pole PFC application. (Figure 5). Here, previous circuits using Si technology have been limited by the slow performance of body diodes in the MOSFETs typically used. A parallel SiC diode helps but defeats the object of reducing component count. Critical conduction mode has had to be used, which sets switching current to zero at the end of each conduction period.

 

Figure 5: SiC devices in a bridgeless totem-pole PFC stage
Figure 5: SiC devices in a bridgeless totem-pole PFC stage

 

However, this variable-frequency mode produces high peak currents with consequent stress, necessitating over-sized components. Using cascode SiC-JFETs, continuous conduction mode can be used with lower peak currents, increasing efficiency, reducing inductor size and easing filtering and EMI problems with fixed operating frequency. An example circuit using USCi UJC06505K devices at 1.5kW and 230VAC-line showed an impressive efficiency of 99.4% [2].

Achieving high efficiency in converter primary switches must be matched with similar improvements in rectification for DC outputs. Again, SiC cascodes fit here as they can be configured for “synchronous rectification” (Figure 6). In so-called third-quadrant operation, current flows from source to drain of one or other of the cascodes through the output inductor to the load during the “forward” and “flywheel” periods of forward or buck-derived converters.

 

Figure 6: SiC cascodes in synchronous rectification
Figure 6: SiC cascodes in synchronous rectification

 

Current flow through the body diode sets the JFET gate-source voltage to approximately +0.7V, turning it naturally hard ON. If the cascode gate is set high, the internal Si-MOSFET channel conducts and the total ON-resistance becomes the RDS(on) of the cascode, giving low conduction losses. Q1 forms the flywheel rectifier and Q2 the forward rectifier.

SiC cascodes are an easy introduction to wide band-gap devices, giving benefits in new designs and as replacements for IGBTs and Si-MOSFETs in legacy systems.

 

References

[1] Micropower Group to sign long term agreement with United Silicon Carbide Inc.

[2] 1.5 kW Totem-pole PFC Using 650V USCi SiC Cascodes

More information: United Silicon Carbide Inc.    Source: Bodo's Power Systems, March 2018