Synopsys and EFPL Partner to Develop Lower-Power Digital Technologies
Researchers from EPFLs integrated systems laboratory (LSI) have developed a way to reduce the power requirement of electronic circuit board chips.
Synopsys, Inc. is a world leader in electronic design automation (EDA) and semiconductor IP. The company also directs its focus on growing software security and quality solutions. This year, Synopsis is adding strength to its academic partnerships. Only recently did the company announce an agreement with EPFL, the Swiss Federal Institute of Technology in Lausanne, Switzerland. Synopsis agreed to license novel digital synthesis technologies from EPFL.
Among Synopsys’ academic partnerships, the University of Rochester and Yokohama National University have been working in congruence to develop a digital circuit design flow for superconducting electronics (SCE). This work is a part of the “SuperTools” program introduced by the Intelligence Advanced Research Projects Activity (IARPA), which is headquartered within the Office of the Director of National Intelligence. The university’s along with Synopsys aim to develop comprehensive software tools for use in the design and analysis of SCEs Very-Large-Scale Integration (VLSI).
EPFLs Method for Designing Lower-Power Circuits
Typically, engineers would use EDA software to construct circuit boards. These conventional software programs translate complex computational models into a vast network of microscopic transistors.
Researchers from EPFLs integrated systems laboratory (LSI) have developed a way to reduce the power requirement of electronic circuit board chips by mapping out and redesigning the logic flows. This enables the generation of a new system with modified logic functions for gates on a multitude of transistors.
It was Dr. Luca Amarù, who was a Ph.D. student at LSI at the time, who endeavored to change the way computer circuits were designed and with determination, succeeded. Amarù devised a new method where he used only two logic primitives: majority and inverter. It was proposed that his new approach would reduce the number of logic steps required to complete a given task. The observation that majority-inverter graph (MIG) optimization reduced the number of logic levels needed by 18% on average when compared to other standard programs was certainly confirmation. This reduction in logic levels frees up transistor capacity for the completion of other tasks. This means that engineers can make their chips smaller, faster, and more efficient.
Amarù’s successes earned him the title of Senior R&D Manager at Synopsys. He went on to further develop a new Boolean algebra for representing the logic functions, which incurred further gains in the efficiency of his circuit system. The advanced EDA and Technology Computer-Aided Design (TCAD) tools introduced by individuals like Amarù are sure to encourage the continued development of more complex, high-speed digital circuits with lower power requirements.
Synopsys are paving the way for a future of smart everything, from silicon to software. Image used courtesy of Synopsys
Technology transfer manager of EFPL, Mauro Lattuada helped arrange the license agreement between EFPL and Synopsys. In a recent news release, Lattuada said that Amarù’s new logic paradigm could certainly “be used for other applications, such as designing and improving FPGAs [field-programmable gate arrays] or searching and analyzing data sets.”