Semitool Patents New Process for Copper Seed Layer Enhancement
Semitool Inc. (Kalispell, MT) announced that it has been awarded a patent for copper seed layer enhancement. The company believes that this advance will aid semiconductor device manufacturers in their drive for higher-performance devices, smaller chips and lower cost from copper interconnect-based semiconductor devices. Semitool reports that its seed layer enhancement technology can extend the application of copper to design rules beyond 0.1µm with current state-of-the-art process technology.
Copper seed layers are deposited on silicon wafers during the manufacturing process by physical vapor deposition (PVD). To minimize seed layer discontinuity, PVD layers are typically deposited at a thickness on the order of 1,000 angstroms. Semitool says that its patented seed layer enhancement technology, however, allows a reduction of PVD layer thickness by as much as 75 percent. The thinner PVD seed layer is then enhanced by Semitool's process, which is claimed to produce higher interconnect yield and improved device performance.