PMBus Details Major Enhancements during Darnell’s Power Forum

It was “standing room only” Thursday, September 12, during the tenth-annual Darnell’s Power Forum (DPF '13) when the PMBus Working Group released the preliminary PMBus V1.3 specifications. PMBus V1.3 (also called “PMBus+” to highlight the extent of the enhanced capabilities and functionality) has broad implications for manufacturers of FPGAs, ASICs, SoCs, networking and communication processors, core processors for computing, server and storage markets, and any other type of core processor that will benefit by adaptively altering its own supply voltage.

The session was started with a discussion of “I2C™ Physical Layer, the Basis for SMBus and PMBus™,” presented by Keith Curtis, Technical Staff Engineer with MicroChip Technologies, Inc. That was followed by “Introduction to the Preliminary Specifications for PMBus™ v1.3 Including new AVS Features,” presented by Michael Jones, Applications Engineer with Linear Technology Corporation, and Travis Summerlin, Director Mixed Signal Design and SMTS with Texas Instruments Inc., both representing the PMBus™ Working Group.

As previously announced, PMBus V1.3 will include: higher speed communication to reduce latencies; a dedicated Adaptive Voltage Scaling (AVS) bus to statically and dynamically control processor voltages; and general enhancements and cleanup from Version 1.2. This presentation added details to that initial announcement, including a 1-MHz Clock, Mandatory Clock Stretching Support and Backwards Compatibility using the same open-drain signaling as the previous PMBus specification. These changes are expected to result in a 2.5-times faster throughput.

PMBus+ supports IEEE 754 industry standard floating point, half-precision, 16-bit numbers; a uniform number system with negative numbers, NaN and +/-Inf and easy conversion to C types. It also supports global process calls, an extension of the SMBus ARA specification and enables intelligent global queries. In the area of applications, it supports device discovery, prioritized fault management and faster bulk reads. In the area of setting relative output voltage thresholds PMBus+ supports margin levels, warn limits, fault limits and power good limits. Values are specified as a percentage of output voltage and changing the VOUT_COMMAND moves all thresholds.

As previously announced, the addition of AVSBus for Adaptive Voltage Scaling is a major change in PMBus 1.3. The AVSBus is behaviorally and electrically similar to SPI bus without chip select lines. In this case, the AVS_MData and AVS_SData are equivalent to MOSI and MISO and the AVS_Clock is equivalent to CLK of the SPI bus. The new specification supports a 50MHz maximum bus speed.

AVSBus commands fall into two broad categories, Feedback from the Slave to the Master and Status responses. Feedback command considerations include: Asynchronous feedback from the slave by pulling low on the AVS_SData line during idle mode indicating VGood OR an Alert has been generated; Every frame start by the master generates a status response from the slave; and Every ACK by a slave is followed by a status response from the slave. Status responses include: VGood – VOUT has reached the target voltage and Alert – One of the bits in the AVSBus Status has been set.

PMBus 1.3 supports AVSBus integration. AVSBus is an application specific protocol to allow a powered device such as an ASIC, FPGA or Processor to control its own voltage for power savings. PMBus is an open standard protocol that defines a means of communicating with power conversion and other devices allowing effective configuration and control as well as telemetry data. The combination of these protocols in a slave device is an efficient and effective solution for systems containing loads that need to adapt the operating voltage.

Finally, the presentation included the anticipated timeline for further refinement of PMBus 1.3. The PMBus Spec Working Group is currently soliciting comments from PMBus Adopters; the period for comments closes December 1, 2013. During January to March, 2014, the working group will develop the final edits to the specification documents with the target release set for APEC 2014.