Renesas Technology Corp. (San Jose, CA), a joint venture between Hitachi Ltd. and Mitsubishi Electric Corp., announced a new stacked chip technology that uses a through-hole interconnection method to enable chips to bond at room temperature. The new technology eliminates the need for wire bonding and reduces package thickness by more than 60% for the most advanced System-in-Package (SiP) products. The method offers a new packaging technology option for developing three-dimensional stacked SiP products.
With this new packaging technique, LSI chips that are between 30 µm and 50 µm thick are fashioned with through-hole electrodes between the top and bottom sides and gold stud bumps. It then allows the bumps and through-hole electrodes to connect by applying a compressive force at room temperature.
Using this technology, the package thickness of a two-layer SiP is reduced by 60% or more, from the current 1.25 mm to 0.5 mm or less. It also enables a package thickness of 1 mm or less to be achieved when stacking 10 LSI chip layers. In addition, chip-to-chip interconnection is performed at room temperature to simplify the manufacturing process.
