Cadence Design Systems Inc. (San Jose, CA) and the Chinese government-founded Shanghai Research Center for Integrated Circuit Design unveiled the ICC-Cadence CPU/digital signal processing SOC reference methodology. The move aims to implement SOC design quickly and meet market timeframes critical for success in China IC markets, according to Cadence.
The reference methodology includes Cadence’s Encounter digital implementation platform, Incisive functional verification platform, and CoWare tools for system-level design and verification. This reference methodology was built upon CPU and DSP cores from processor IP providers, while the implementation flow was validated with several foundries on their 0.18-micron processes.
