Toshiba Develops New 8-Bit Core for Next-Generation Microcontrollers
Toshiba America Electronic Components, Inc. (TAEC) announced that Toshiba Corp. (Toshiba) has developed a new 8-bit microcontroller (MCU) core. Designated TLCS-870/C1, the new core is capable of processing one instruction cycle in a single clock cycle, enabling faster processing at lower frequencies, reduced noise and lower power consumption compared with Toshiba's previous 8-bit core. Its large-capacity address space is expandable to 128kB. The flexible TLCS-870/C1 core is well suited for a wide range of applications from small-scale applications, such as portable digital-consumer products, to large-scale applications requiring large-capacity ROM, such as air conditioners, washing machines, and other white goods.
"Toshiba's new TLCS-870/C1 core heralds the beginning of a new concept of 8-bit MCUs," said Roland Gehrmann, business development manager in the ASSP Business Unit at TAEC. "Our next-generation TLCS-870/C1-based 8-bit MCUs will offer low power, low voltage and performance comparable to that of 16-bit devices. In response to customer feedback, the new family will help reduce system cost by integrating must-have features such as a voltage-detection circuit, a power-on reset circuit, and an on-chip debug circuit." TAEC plans to introduce its first new products based on the new core in the fourth quarter of 2006.
The core architecture was modified from the previous TLCS-870/C architecture to achieve the fast processing of one instruction cycle in a single clock cycle. The result was up to a four-fold increase in performance at the same clock frequency, compared with existing Toshiba 8-bit MCUs. Part of the IC design used synchronous RTL design instead of multiphase-clock design based on circuit diagrams.
The expanded address space was attained with a memory-management method that manages code and data in separate areas. Up to 128kB of address space can be implemented in an 8-bit MCU without any adverse consequences such as increased footprint due to address-bus expansion or degraded processing speed, which is common with the alternative memory-bank method.
The TLCS-870/C1 core is binary compatible with previous Toshiba 8-bit MCUs; thus, existing software resources can be used. When used in combination with a Toshiba C compiler, high code efficiency can be realized.
