Maximizing Value: How 3-Level DC-DC Converters Reduce BOM and System Cost

Modern power delivery systems face two conflicting demands: higher performance and lower cost. Whether powering next-generation consumer electronics, power tools, or high-wattage USB-PD devices, engineers must squeeze more efficiency into smaller, more affordable designs. One emerging answer is the 3-Level DC-DC converter architecture, which can deliver impressive efficiency gains while cutting bill of materials (BOM) cost and reducing board size.

Why a 3-Level DC-DC?

A 2-Level Buck controller uses two FETs (external or internal) and a single inductor for power transfer. These are called 2-level controllers because the inductor phase node (V_SW) swings between VIN and ground—just two levels. In this topology, the FETs must block the full VIN voltage when turned off, and the inductor ripple peaks at a 50% duty cycle.

Figure 1. A typical 2-Level DC-DC topology

The three-level (3L) buck converter consists of two additional switches and a flying capacitor compared to a conventional two-level (2L) buck converter. Switches Q1 and Q4 are out of phase, and similarly, Q2 and Q3 are out of phase. The switching node (V_SW) alternates between VIN and VIN/2, or between VIN/2 and ground—hence the name ‘3-level.’

Figure 2. A typical 3-Level DC-DC topology

In steady state, the flying capacitor holds VIN/2, reducing voltage stress on the switches. This allows the use of lower-voltage FETs with better figure of merit , which leads to reduced conduction and switching losses proportional to V².

This topology also enables the use of a smaller inductor, as the inductor sees only half of VIN. The inductor ripple occurs at twice the FET switching frequency, causing the peak-to-peak ripple to be only one-quarter of that in a 2-level converter—resulting in reduced inductor core and DCR losses.

Figure 3. Inductor ripple vs. duty for 2 and 3 level buck converters

BOM Reduction Opportunities

By leveraging the improved thermal and electrical efficiency of 3-Level designs, engineers can:

• Downsize inductors and capacitors without compromising performance.
• Reduce component count by simplifying snubber circuits and EMI filtering.
• Select lower voltage-rated MOSFETs, which are more cost-effective and have lower conduction losses.

   

Real-World Application Examples

USB-PD Multiple-port Chargers

In high-wattage USB-PD (especially EPR >65 W), efficiency and thermal management are critical. A 3-Level DC-DC converter can operate at higher switching frequencies without penalty, enabling smaller magnetics and faster transient response. The reduced heat load allows for sleeker, fanless enclosures, directly lowering manufacturing and materials cost.

Figure 4. USB-PD multiple-port charger with 3-level DC-DC diagram

Consumer Power Products

For products like laptops, docking stations, and high-end portable audio gear, board space is often at a premium. A smaller power stage not only reduces BOM cost but also frees up room for additional features, better aesthetics, or a smaller overall form factor. Featuring an innovative power stage design incorporating a 3-level switch node and a 2-level switch node across the inductor, this architecture enables buck, buck-boost, or boost mode.

Figure 5. Consumer power product with 3-level DC-DC diagram

Voltage Derating Advantages

Because each component in a 3-Level converter experiences a lower voltage swing, voltage derating requirements are eased. For example, in a 2-Level buck converter stepping 24 V down to 5 V, the high-side MOSFET might see the full 24 V during off-state, requiring a 30 V–40 V device with higher R_DS(on) and cost. In a 3-Level topology, the MOSFET only sees about half that (≈12 V), enabling the use of a 15 V–30 V MOSFET with much lower R_DS(on), better switching performance, and lower cost.

This effect cascades through the design — reduced voltage stress allows designers to pick from lower-voltage, higher-performance component families, which often have better figures of merit (FOM) and lower conduction and switching losses. The net result is a smaller, cooler, and less expensive power stage.

Inductor Size and Efficiency Advantages

Because the ripple current in a 3-Level converter is naturally reduced, the inductor size requirement is eased. For example, in a 2-Level buck stepping 24 V down to 12 V, the inductor must handle the full 24 V to 0 V transition across each cycle. This results in higher peak-to-peak ripple current, forcing designers to select larger inductance values and physically bigger inductors with higher core volume and copper windings. Larger inductors not only increase cost but also introduce higher DC resistance (DCR), which adds conduction losses and further lowers efficiency.

In a 3-Level buck, the effective voltage across the inductor is cut in half because switching transitions occur between intermediate voltage nodes (≈12 V to 0 V or 24 V to 12 V). This reduces ripple current nearly by 50%, allowing a smaller inductance value to achieve the same current ripple.

Smaller inductors with lower DCR lead directly to reduced conduction losses, faster transient response, and a more compact design. At the same time, lower ripple reduces output capacitor stress and improves system reliability. The combined result is higher efficiency, smaller footprint, and lower overall system cost, making the 3-Level topology especially attractive for high-current, space-constrained applications.

System-Level Impact

Switching to a 3-Level DC-DC architecture is not just a component-level change—it has system-wide implications that can cascade into measurable benefits across the entire product design."

• Lower Thermal Design Requirements

Because the 3-Level topology reduces switching and conduction losses, less heat is generated in the power stage. For example, in a 200 W USB-PD charger, the thermal dissipation could drop by 1–2 W compared to a 2-Level design. This may allow you to replace a bulky aluminum heatsink with a smaller stamped-metal part or even remove it entirely, eliminating the need for thermal pads or heat pipes and reducing BOM cost and assembly complexity.

• Smaller PCB Area Dedicated to Power Conversion

With lower losses and voltage stress, inductors and capacitors can be physically smaller. In a typical notebook adapter, the power stage area might shrink by 20–30%, freeing up valuable board space for additional ports, wireless charging coils, or enhanced mechanical design. Smaller components also allow for higher component density, making it easier to meet enclosure size or weight targets.

• Higher Efficiency Leading to Lower Operating Costs for the End-User

In high-volume consumer devices, even a 0.5–1% efficiency gain translates into tangible energy savings over the product’s lifetime. For example, a 95% efficient 3-Level 240 W USB-PD charger will waste 12 W less power per day than a 93% efficient 2-Level design when operated at full load for eight hours—reducing electricity costs and heat buildup for the end-user. This is particularly important in enterprise or data-center environments where dozens or hundreds of such units may be deployed.

High Performance, Cost-Optimized

The 3-Level DC-DC converter offers a compelling way to maximize value in power delivery systems. By cutting BOM cost, shrinking component size, and simplifying thermal management, this topology enables designers to deliver high-performance, cost-optimized products that meet the demands of modern applications. As USB-PD and other high-power markets continue to grow, the 3-Level approach will become an increasingly attractive option for engineers focused on both performance and profitability.

All images used courtesy of Renesas.