Industry Article

Maximizing the Efficiency of Totem Pole PFC Stages Using SiC FETs

The Totem Pole PFC circuit promises a significant improvement in AC-input converter efficiency, but limitations of mainstream semiconductor switch technologies have not allowed full potential to be reached. SiC FETs however overcome these limitations and this article describes how efficiencies of over 99.3% can be realized at multi-kilowatt levels.

Designers of AC-input power supplies have to wrestle with many requirements, from functional to safety, EMC and more. Often trade-offs are necessary and a good example is the need to hit efficiency targets such as the ‘Titanium’ standard for server power supplies while keeping line harmonic emissions low with power factor correction (PFC), to help power grids operate reliably and efficiently. PFC is practically implemented in most cases by a boost converter which steps up rectified mains to a high DC voltage, with pulse width modulation forcing the line current to follow the sinusoidal waveshape and phase of line voltage. A PFC stage inevitably has losses though, so much effort has been expended in designs to increase efficiency, with a figure better than 99% deemed to be the minimum acceptable from AC input to high-voltage DC.

The Totem Pole PFC Stage Has Fewer Components in the Conduction Path

A bridge rectifier providing rectified AC to a separate boost stage, Figure 1 (left), has been widely used for active power factor correction, but losses in the diodes alone can easily exceed the overall 1% budget. A better solution is the Totem Pole PFC stage (TPPFC), Figure 1 (right). 

Figure 1. Bridge rectifier input (left) and totem-pole PFC stage (right) 


In the TPPFC circuit, when the AC mains connection to L1 is positive, Q1 forms the boost switch, Q2 forms a synchronous rectifier, Q3 conducts to allow line current to circulate and Q4 is blocking. When the AC input is negative Q1 and Q2 swap roles, Q3 blocks and Q4 conducts. At any time, in the TPPFC stage, one fewer device is conducting compared with the bridge input PFC and the overall voltage drop is lower still because all the diodes are replaced by synchronous rectifiers. Q1 and Q2 switch at high frequency as in a normal boost converter but Q3 and Q4 conduct alternately at line frequency so only their conduction losses are critical.

PFC Stage Conduction Mode Must be Chosen

Designers have a choice of operating mode with any boost converter, relating to whether energy stored in L1 is fully transferred to the output or not, each cycle. This corresponds to inductor current falling to zero each cycle (discontinuous conduction mode, DCM) or remaining positive (continuous conduction mode, CCM). The circuit can also be arranged to operate on the borderline between the two, (critical conduction mode, CrM) requiring variable switching frequency overload and line variations. The modes have different pros and cons; DCM circuits have soft turn-on switching for low losses but high dV/dt-related EMI on turn-off and excessive peak current levels that make the mode impractical for high power applications. CrM has the disadvantage of variable frequency operation and although peak currents in CrM are lower, they still produce unacceptable conduction losses unless stages are interleaved with the associated cost and complexity. CCM peak current is the lowest with least conduction losses, but the circuit is ‘hard switching’ with turn-on and turn-off while significant current is flowing, leading to potentially high losses if using power switches based on Si. Major contributors to these losses are the reverse recovery of the high-frequency boost synchronous rectifier body diode QRR and the output capacitance COSS of the boost switch which has to be charged and discharged each cycle. The effects can be so severe that until relatively recently, the topology has not been seen as viable with semiconductor devices available. 

Wide Band-gap Semiconductors are the Solution

Silicon carbide (SiC) and gallium nitride (GaN) are seen as the future of power semiconductors and much has been written about their headline benefits of low on-resistance and low switching loss. Naturally, they have been considered for the TPPFC circuit and indeed do make the circuit viable. SiC MOSFETs perform better than silicon MOSFETs, with 80% or more reduction in body diode reverse recovery charge QRR and lower output capacitance COSS. However, the body diode has a very high forward voltage drop during ‘dead time’ before the synchronous rectifier conducts. Gate drive with SiC MOSFETs is also sometimes problematic with threshold hysteresis and variability, along with a small margin between gate voltage for full enhancement and the absolute maximum.

GaN devices have no body diode and no reverse recovery problems but gate drive is complex for optimum efficiency with a low threshold voltage risking spurious turn-on. GaN HEMT cells are also still relatively expensive and rated for lower power ranges with no avalanche capability.

SiC FETs are Better Still

A device that keeps the best aspects of a SiC MOSFET but without the disadvantages is the SiC FET, a cascode combination of a high voltage SiC JFET and a low voltage Si-MOSFET. The device is fast with very low ON-resistance but has an easy gate drive, compatible with Si-MOSFETs or even IGBT levels. Threshold voltage is high, with no hysteresis and good margin to the absolute maximum ratings. The device has a body diode effect defined by the low voltage Si-MOSFET which has extremely low QRR and a forward drop of only around 1.75V while output capacitance COSS is low. There is an avalanche effect that protects against overvoltage.

The SiC FET has been pioneered by United Silicon Carbide and is now in its fourth generation which shows improved cell density to reduce on-resistance per unit area (RDS.A) and advanced thermal design with silver sinter die-attach and wafer-thinning techniques for minimum thermal resistance to the substrate.

Comparisons are only meaningful between SiC FETs and other technologies for the same voltage class of device and when characteristics that are traded-off are factored in. It is therefore useful to look at figures of merit such as RDS.A for die per wafer at a given performance and RDS.EOSS, a measure of how hard-switching losses are traded against conduction loss. Figure 2 shows the comparisons between a 750V Gen 4 UnitedSiC SiC FET device and 650V SiC MOSFET competitive parts at 25°C and 125°C. The benefits are clear, along with the useful extra 100V in rating of the SiC FETs.


Figure 2: SiC FETs compared with SiC MOSFETs


Practical Results Prove SiC FET Advantages

UnitedSiC has built a totem pole PFC stage demo board using their Gen 4 UJ4C075018K4S devices, rated at 750V and 18 milliohms in TO-247-4L kelvin-connection packages. The PFC stage is rated at 3.6kW 85-264VAC input and 390VDC output.  Two of the SiC FETs are used for the 60kHz high frequency switching leg and four 28 milliohm silicon Superjunction MOSFETs are used for the ‘slow’ leg. Figure 3 shows the efficiency curves, peaking at 99.37% at 2.5kW output at 230VAC. For information, curves are also shown for lower-cost 60 milliohm SiC FET devices with two in parallel in each position.

Figure 3: Efficiency of a 3.6kW totem pole PFC stage using SiC FETs


For very cost-sensitive applications, Q3 and Q4 in Figure 1 could be replaced with standard silicon diodes and efficiency can still exceed 99% in the demo board described. If a bridge rectifier is used, the extra two diodes can usefully be used for inrush protection to prevent momentary saturation of the boost inductor on startup.


Using the FET-Jet calculator

To make the selection of appropriate SiC FETs easy, UnitedSiC has made a web-based design tool available, the FET-Jet calculator. The interactive tool includes pre-programmed application circuits for isolated and non-isolated DC-DC converters of different topologies and AC-DC converters, including the simple boost PFC, totem-pole PFC, and others. CCM and CrM modes are supported.  SiC FETs can be selected from a drop-down list for each application and the tool instantly calculates overall efficiency, losses analyzed by switching and conduction contributions, junction temperatures, and current stress levels. Devices can be selected to be paralleled for higher power and warnings are given for invalid inputs. The tool is free-to-use with no registration required.

The totem pole PFC stage has been a tantalizing approach promising higher efficiency and simpler design, but until recently semiconductor technology has not allowed it to reach its full potential. With SiC FETs the circuit now can form part of an engineer’s armory to reduce power losses to even lower levels in AC input converters.