Dealing with CommonMode Voltage Influence

The extreme signal rise-time made possible by wide-bandgap semiconductors create common mode voltages at the switching frequency and above. Without appropriate measures, instrument readings will show huge deviations from the true value. We will present possible approaches to address this challenge and discuss their relative merits.

The quest for clean and sustainable sources of energy has always been accompanied by a race for more efficiency. Clean production of energy needs to go hand in hand with avoiding waste of energy. Since electric motors and motor-driven systems account for about 40% of the global consumption of electricity, switching to variable-frequency drives carries enormous potential for energy savings. Advances in semiconductor technology – like SiC and GaN – allow the construction of ever more efficient frequency converters and inverters, helping to close the gap between green production and overall consumption.

Unfortunately, the increase in efficiency is paid for with downsides on the signal side: increased switching speed results in extremely steep rising and falling voltage flanks, which in turn can cause severe common-mode issues. In this article, we will focus on the consequences of common-mode voltages for accurately measuring power and efficiency.

Figure 1: Example PWM signal

The CMRR is defined as the ratio of the powers of the differential gain over the common-mode gain, measured in positive decibels. This definition is geared towards amplifiers, but we can redefine the CMRR in a wider sense to look at how well an instrument can deal with common mode influence. In the instrument, the rather symbolic “gain” can be defined as the ratio between the amplitude applied to the measurement channel input and the result displayed on-screen; it thus equals 1. It has to be noted, however, that the susceptibility of an instrument to common-mode influence is not a direct consequence of the CMRR of its op amps, since those never get exposed to common-mode signals in the first place. Rather, the CMRR is a consequence of a variety of asymmetries in the analog design, differing path lengths, stray capacitances etc. Leaving the root causes aside, we will look at three differing approaches found in the market to deal with the issue:

Approach #1: The obvious approach is the choice of an instrument (e.g. a power analyzer or an oscilloscope) that already offers an excellent CMRR. In terms of complexity and usability this choice has clear advantages over more intricate solutions, and it can also easily be handled by less experienced users. However, not all instrument manufacturers even specify their CMRR, so it might be difficult to get the required information for selecting the appropriate model in the first place. It is important to read the specification correctly: what matters is the CMRR at the desired operating point, which might be considerably worse than the one typically specified at 50/60Hz.

Approach #2: The use of an artificial star point for measuring three-phase systems. This approach is low-cost and trivial to implement, it merely requires an additional piece of hardware (basically a combination of three resistors) between the instrument and the DUT. Unfortunately, it does nothing to mitigate common-mode issues when measuring signals with high du/dt values, as can easily be demonstrated by monitoring the voltage of the star-point. It still occasionally being implemented probably stems from the confusion of the influence of the phase voltages with that of the switching pulses. The former are not significantly relevant for common-mode issues.

Figure 2: Star-point floating voltage

Approach #3: The use of high-quality differential probes can eliminate common-mode problems, 
as long as the specified CMRR is sufficient - the same considerations already listed in the paragraph about CMRR in instruments apply. The cost impact is considerable and needs to be taken into account when playing with the idea to save budget by going for a low-cost instrument with poor “built-in” CMRR. Of course, in many cases existing probes that are also used for non-power measurements could be re-purposed for the job – although this might create conflicts when calibrated measurements are required, as we will see below. The addition of probes, does however, add complexity to the measurement setup. This needs to be taken into account both when calculating the uncertainty of the measured results and when calibrating the system. Strictly speaking, the system should get calibrated as a whole, and for the results to remain valid it must not be modified in any of its parts – the probes need to stay attached to the channels they were connected to during calibration. This is rarely ever the case in practice, though. Typically, all components get calibrated separately, often at different times and maybe even different points of operation. To calculate the correct measurement uncertainty for the combination of all parts of the chain can become a laborious task that needs to be carried out painstakingly in order to obtain valid results.
Whether CMRR gets optimized in the instrument itself or its measurement accessories, there is a relatively straightforward test to judge the effectiveness of the measures taken. In the first step, the voltage input of the instrument needs to be shorted in order to eliminate any difference in potential. The area of the conductor loop used for the purpose needs to be kept minimal in order to avoid unwanted inductive coupling of leakage currents to earth. Once inputs are shorted, the voltage reading needs to be written down (U1). It basically shows the combination of the DC offset and the noise floor of the measurement channel. Next, the phase voltage of the DUT, e.g. an inverter, needs to be applied to one input. 

Figure 3: CMRR measurement setup

From this point on, said input will float up and down with the common-mode voltage. Again, the resulting voltage reading needs to be recorded (U2). From these two values, the common-mode voltage (UCM) can easily be calculated:

`U_("CM")=  √((U_2)^2-(U_1)^2 )`

With typical values of U1=9mV and U2=21mV we thus obtain: 

`U_("CM")=  √((21"mV"_2)^2-(9"mV"_1)^2 )=19 "mV"`

Accordingly, the common-mode rejection at a phase voltage of 180V with a real-life frequency mix can be calculated for this example as:

`CMRR =20*log⁡(U_("cm")/U_("phase") )=0.019V÷180V ≈ -80dB`

The obtained value of -80dB is excellent for a realistic PWM signal with steep edges. When comparing data sheets of different instruments you will observe that many models struggle to beat this result even with a rather benign sinusoidal signal at 50/60Hz that completely avoids sharp voltage peaks. 

Take-home messages: 

With GaN/SiC, CMRR becomes more important than ever for power analysis.

Too narrow focus on cost optimization will be punished by compromised accuracy.

It is up to the user how much to invest in the core instrument vs. peripheral equipment.