Driving Lasers: Chasing the Speed of Light
As the level of automation increases in machines, detailed awareness of the surroundings becomes necessary. Time-of-flight-based 3D imaging systems have become the eyes of machines. eGaN® technology has been the workhorse of laser drivers for these systems, enabling the resolution to make intelligent decisions.
When you are chasing the speed of light at tens to hundreds of amps from tens to hundreds of volts, there is little room for parasitic capacitance and inductance. This article explains the detailed mechanisms for driving lasers and why eGaN FETs and eToF ICs have been and will continue to be the best choice for these demanding applications. It should be noted that the concepts presented in this article can be applied to most power-switching applications.
Fundamentally, the circuit for driving a pulsed laser for time-of-flight lidar is simple, as shown in Figure 1. While other circuits are possible, they need more and larger components and have a higher cost. With optical power being related to laser current, the electrical objective is to achieve the required peak current in a time on the order of the speed of light relative to the required resolution. Considering light travels 0.3 m in 1 ns, inductance must be kept on the order of hundreds of pH to keep the driving voltage at a practical level, and the driving voltage must be applied in hundreds of ps.
Figure 1. Basic laser driver circuit. Image used courtesy of Bodo’s Power Systems [PDF]
Much has been written of techniques to reduce inductance to hundreds of pH using short, wide traces and inductance cancellation. The focus is on the laser driver, which must apply the voltage to the power loop inductance fast enough to achieve the required peak current. In the sub-nanosecond timeframe, at the currents required to achieve the system's distance and field of view, the charging and discharging of the multiple capacitances and their overlapping loops must be considered in detail, as shown in Figure 2.
Figure 2. Detail of laser driver loops and stray elements. Image used courtesy of Bodo’s Power Systems [PDF]
Figure 3 shows an approximation of key waveforms for a turn-on event for the circuit of Fig. 2. Turn-on starts with the logic input going high. After some propagation delay, the gate voltage rises with CGS charging through the various impedances of the turn-on gate drive loop, as shown by stage 1. Even with the gate voltage rising, there is negligible impact on the laser power loop until VGS reaches a value where the output FET begins to conduct. With the laser driver's extreme di/dt and dv/dt, the input loop must be decoupled from all other loops through layout and/or filter to prevent false triggering. It should be noted that that the return to the gate drive capacitor in the turn-on gate drive current loop comes from the power FET source and not the gate driver, as shown in Figure 2. Figure 4 shows the transfer characteristics of the EPC2204. This curve defines the VGS necessary to begin conduction and the VGS necessary to drive the required current. In this example, 1.75 V is necessary to begin conduction. This is where stage 2 of Figure 3 begins.
Figure 3. Theoretical waveforms, laser driver turn-on. Image used courtesy of Bodo’s Power Systems [PDF]
With the FET channel beginning to conduct current, COSS starts to discharge, and VDS begins to fall. Driven as a step pulse, VDS must collapse rapidly to present a high voltage across the power loop inductance that drives the di/dt of the resonant circuit that determines the magnitude and duration of the pulse for the application. Since channel current, hence dv/dt, is controlled by the transfer characteristics curve, VGS must continue to increase to accelerate COSS discharge. In this stage, discharging CGD is added to the burden of the gate drive loop. As soon as VDS begins to fall, laser current begins to rise. At this point, there is an interaction between the gate drive and power loops. Inductance common to these loops, known as common source inductance (LCS), carries the di/dt of the power loop resulting in a voltage drop that is subtracted from the gate drive potential, slowing the gate capacitance charging. It is critical to separate these loops as much as possible, as even common source inductance values of 100 pH can result in large increases in turn-on time.
Figure 4. Transfer Characteristics of EPC2204. Image used courtesy of Bodo’s Power Systems [PDF]
Figure 5. Top board layer layout. Image used courtesy of Bodo’s Power Systems [PDF]
Stage 2 is completed when COSS is discharged, and VDS has collapsed completely. At this point, full laser drive voltage is applied across the power loop inductance resulting in maximum di/dt. Minimizing LCS is very important because with 25 pH at 100 A/ns gives a 2.5 V drop. For a 5 V gate drive, this leaves 2.5 V of gate drive potential, which will limit gate current and switching speed. Achieving a low LCS requires a low inductance package and careful attention to layout where the two loops that contribute to common source inductance need to be separated right at the package, as shown in Figure 5. In addition, wire bonds and clips in the source add inductance and thus are not suitable packaging options.
Stage 3 requires the current in the laser to reach the required value and, thus, VGS must continue to rise past the voltage necessary to achieve full current based on the transfer characteristics curve. Taking EPC2204 as an example, 80 A requires VGS > 3 Vat 25 °C and > 3.7 at 125 °C, stressing that the voltage induced by the power di/ dt over LCS will be subtracted from VGS. Stage 3 is completed when the laser achieves the full required current, typically at the peak of a resonant pulse in the case of a resonant laser drive topology where the laser drive capacitance and the power loop inductance form an LC tank. In this case, the LC determines the pulse width, together with the laser drive voltage, controls the peak current and optical power . In the case of an active turn-off topology, full current is reached when the laser voltage plus the laser driver voltage equals the laser drive source voltage. Figure 6a shows example waveforms of a resonant discharge laser driver with the yellow trace being laser current and dark blue trace representing optical power. Figure 6b shows example waveforms of an active turn-off laser driver with the blue trace representing optical power and the red trace being drain voltage.
Image used courtesy of Bodo’s Power Systems [PDF]
Figure 6. Laser driver waveforms of a. resonant discharge topology and b. active turn-off topology. Image used courtesy of Bodo’s Power Systems [PDF]
For turn-off, in the resonant case, the laser driver is turned off close to or at zero current and must be low enough that the drain capacitance is mostly discharged but does not ring. Active turn-off manifests as a classic ZVS turn-off, with the laser driver disrupting the power loop, diverting current of the power loop into the COSS. Its rise in voltage across the power loop inductance drives the turnoff of current. A similar loop analysis to turn-on must be made for proper design.
Laser Driver Selection
Laser driver selection starts with determining the best semiconductor technology and packaging for an extreme combination of speed and power. Packaging must have low inductance, but more critically, low common source inductance. Wafer-level packaging provides the minimum inductance possible. Integrating the gate drive with the power FET, such as EPC’s EPC21701 eToF™ laser driver, shown in Figure 7, reduces the number of package connections and board traces, reducing inductance and greatly reducing common source inductance. It also matches the gate driver to the power FET, which can enhance performance and reduce cost. It also reduces the size of the laser driver circuitry, which is especially important for multichannel lidar systems.
Figure 7. Bump side image of 1.7 mm x 1 mm EPC21701. Image used courtesy of Bodo’s Power Systems [PDF]
The semiconductor technology chosen must have the lowest capacitance per peak current for the required voltage. eGaN technology has QGS and QGD an order of magnitude lower than comparable silicon MOSFETs, and about half the QOSS, which together with the low resistance of the metal gate, ensures the fastest possible switching speed. Once the technology is selected, peak current must be correctly sized. A device that is too small does not provide sufficient output power; a device too large results in a slower driver due to excess capacitance (and higher cost). The transfer characteristics curve, over the necessary temperature range, drives the selection.
Fundamentally, eGaN technology has vastly lower capacitance when compared with silicon MOSFET alternatives. Integration of the gate driver and chip-scale packaging greatly reduces inductance and allows one to take full advantages of their inherently high speed. Along with a low inductance layout, one can increase power and reduce pulse width of the optical pulse resulting in increased resolution, range, and field of view while reducing power consumption in ToF imaging systems, where the metric is the speed of light.
This article originally appeared in Bodo’s Power Systems [PDF] magazine.