Building Higher Reliability Power MOSFETs at a Lower CostSeptember 12, 2016 by Sujit Banerjee
This article discusses the advantages and the promising benefits of SiC MOSFETs for power conversion systems in PV inverters, data centers, and more.
Since their initial release to the market four years ago, several factors have slowed the commercial adoption of silicon carbide (SiC) MOSFETs, including their high cost (more than five times that of silicon IGBTs) and uncertainty toward their reliability, parametric stability and lifetime.
Despite these concerns, a growing number of power electronics systems manufacturers are turning to SiC power MOSFETs to balance their needs of greater efficiency, power density, and reliability with the natural desire for lower cost devices.
To encourage broader use of this revolutionary technology, SiC MOSFET manufacturers must be able to provide power electronics designers with devices that bring together a stable threshold voltage, a suitably long gate oxide lifetime, and last but not least, competitive pricing. For some manufacturers, this may require a fundamental rethinking about how and where to produce their products.
This rethinking may involve two central approaches. First, developing design and process techniques that are compatible with processes in a conventional silicon CMOS fab will serve the dual purposes of eliminating the capital expenses associated with launching a dedicated SiC facility as well as leveraging economies of scale in an incompletely filled fab. Second, producing devices on 150 mm (6 inch) SiC wafers rather than 76 mm (3 inch) or 100 mm (4 inch) SiC will allow two to four times as many devices produced per wafer (assuming yields and substrate thickness are the same).
Indeed, more than ninety percent of SiC device processes are compatible with processes already available in a silicon CMOS fab. By integrating the process flows for both silicon and SiC wafers and running them in parallel, one may take advantage of substantial economies of scale. The approach, which was recently employed to produce 1200 V SiC MOSFETs in an automotive-qualified 150 mm CMOS fab, has created devices that demonstrate high manufacturability, excellent device performance, highly reliable gate oxides, and robust parametric stability at operating junction temperatures of 175 °C.
Although SiC is fundamentally compatible with most CMOS fab processes, a number of significant hurdles must be overcome in order to realize this approach, particularly including requirements for high-temperature processing. Other challenges include integrating CMOS- and SiC-specific process steps, as well as making metal and dielectric stacks used in the SiC MOSFET compatible with a conventional CMOS fab. Whenever possible, standard process steps available in a CMOS foundry should be used with SiC wafers, such as implantation masks and toplevel interconnects.
For steps such as gate oxidation and metallization, SiC-specific processes may be developed using CMOS production tools such as high-temperature furnaces and Rapid Thermal Processing ovens, but dedicated tools are required for implant activation and certain ion implantation steps. Mechanical wafer handling procedures also require modification due to the semi-transparency of SiC wafers. For example, sensors set up for use with opaque materials respond incorrectly when used with SiC, leading to wafer breakage during loading/unloading. Automated defect detection tools can confuse sub-surface features with surface defects, and differences in wafer thickness can further complicate wafer handling. Nevertheless, with proper process modifications, SiC and Si wafers can be run in parallel in a high-volume production environment, taking advantage of the less costly production processes running in the CMOS fab.
Figure 1: Impact ionization contours at device breakdown. To ensure stable avalanche breakdown, the device was designed to break down at the center of the unit cell.
Producing rugged SiC MOSFETs with wide process margins requires ensuring stable and uniform avalanche breakdown in the device unit cells, avoiding high fields in the oxide, and breakdown in the edge termination. Optimally, device termination should achieve close-to-ideal parallel plane breakdown voltage over a broad dose range, providing a wide process margin. In addition, the JFET region of the device under oxide must be optimized with proper doping concentration and physical dimensions.
Figure 1 shows an example of impact ionization contours at device breakdown. In this case, the device was designed to preferentially break down at the center of the unit cell, ensuring uniform avalanche conditions and a low peak field in the oxide. Other important device and process design modifications include optimizing the channel and P-well designs to ensure the device remains off over the entire voltage and temperature envelope.
Figure 2 presents the typical off-state IV (VGS = 0) characteristics of the fabricated MOSFETs from 25 °C to 175 °C with low leakage current (<100 µA) over a worst-case voltage and temperature envelope. Figure 3 compares the forward characteristics of these devices at 25 °C and 175 °C. The typical on-resistance of these MOSFETs at VGS = 20 V, 25 °C is 65 mΩ. Although these devices were optimized for robustness and manufacturability, the typical specific ON-resistance, Rsp, (normalized to the devices’ active area) is competitive with that of other 1200 V SiC MOSFETs now on the market. With more aggressive processes and designs, it has proven possible to achieve Rsp of 3.1mΩ-cm2 on an identical process platform.
Figure 2: Typical forward characteristics (IDSS; VGS = 0) of manufactured MOSFETs for temperatures from 25 °C to 175 °C. Low leakage current up to 1200 V and 175 °C, entire operating envelope.
Figure 3: Forward characteristics at 25 °C (left) and 175 °C (right).
Reducing SiC MOSFET production costs requires a highly manufacturable process with sufficient margin. To evaluate the manufacturability of the process, the breakdown voltage distribution of a large quantity of devices from multiple wafers from different fab lots was analyzed. The analysis showed that the process provided sufficient margin to accommodate a wide range of epilayer doping variations. Because 100 mm SiC wafers remain more common than 150 mm SiC wafers, the diode leakage current of the fabricated devices was also investigated to assess defect density and device yields. Diode leakage wafer maps revealed only randomly located failures and yields of greater than ninety percent.
The ruggedness of the devices produced was evaluated with various techniques, including sourcing a constant current of 10 mA into the drain for 10 seconds in the OFF state and in avalanche condition. Results showed the devices were extremely robust with stable and uniform avalanche (Figure 4).
Because gate oxide quality is a common concern for SiC MOSFETs, Time Dependent Dielectric Breakdown (TDDB) measurement of capacitors at high temperatures was previously used to study the fundamental quality of the gate oxide process. Charge-to-breakdown (QBD) measurements in large area DMOSFETs produced QBD values well above 10 C/cm2 and no defective tail that would indicate intrinsic failure modes. High-temperature Gate Bias (HTGB) testing at VGS of -10 V and +20 V showed excellent threshold voltage stability. When the MOSFETs were subjected to 1400 hours of high-temperature (175 °C) reverse bias (HTRB) testing at VDS = 960 V and VGS = 0 V, stable breakdown voltage characteristics were observed.
Figure 4: Breakdown voltage vs. time testing demonstrated that the process produced robust devices with stable avalanche characteristics.
High power SiC MOSFETs hold enormous promise for the continuing development of compact, high efficiency power conversion systems in applications like photovoltaic inverters, datacenter power supplies and electric vehicle chargers. Looking further ahead, there will likely be opportunities in automotive traction inverters and motor drives. However, to turn these opportunities into reality, prices must come down substantially. Innovative techniques like producing them in high-volume, automotive-qualified 150 mm CMOS fabs could cut SiC MOSFET costs by 80 percent within five to eight years, allowing them to achieve price parity with silicon IGBTs and encouraging their wider adoption.
About the Authors
Sujit Banerjee is CEO and founder of Monolith Semiconductor Inc., which focuses on commercializing and enabling widespread adoption of SiC power semiconductors. He holds a PhD from Rensselaer Polytechnic Institute, and has been awarded more than 25 patents for his work in power semiconductors.
Kevin Speer joined Littelfuse in January 2015 as Global Manager of Technology Strategy, providing direction for the growth and trajectory of the company’s power semiconductor business and roadmaps. He holds a BSEE from the University of Arkansas, and an M. Eng. and a PhD from Case Western Reserve University.
This article originally appeared in the Bodo’s Power Systems magazine.