Bond Buffer – Increase Power Density and Lifetime without Changing the System
This article discusses Danfoss Bond Buffer Technology and its impact on improving power density and lifetime of power modules without changing the system.
The increasingly ambitious requirements of the automobile and renewable energy markets demand that power modules must increase in both power density and lifetime. State-of-the-art module concepts have reached their limitations in terms of power density, current carrying capability and reliability. Connection technologies for the chips are a bottleneck for their performance.
A new bonding and joining technology for power modules has been developed to address this demand, where the solder joint between the DBC-substrate and the chips is replaced by a sintered joint. In addition, a copper plate is sintered on top of the chip surface metallization, and traditional aluminium bond wires are replaced by copper wires.
The combination of these improvements - sintered connection between chip and DBC-substrate, the sintered copper Bond Buffer and copper bond wires - is known as Danfoss Bond Buffer (DBB) technology.
To study the influence of this new technology on various electrical parameters, four different types of test devices were assembled, each differing in one single detail. All chips were wire bonded with 8 stitched bond wires (300µm), with 2 bond feet on the chip surface – a total of 16 bond feet per chip. To minimize the influence of the scatter- ing parameters, all chips were picked from just one wafer.
Figure 1: Overview of test devices and results of comparison
Test device 1 represents the current state-of-the-art assembly and interconnection technology. Device 2 consists of a chip which is sintered to the DBC. Device 3 consists of a chip which is sintered to the DBC and has a sintered bond buffer on the top and aluminium bond wires. Device 4 represents Danfoss Bond Buffer technology (i.e. sintered connection between chip and DBC-substrate, the sintered copper Bond Buffer and copper bond wires)
Thermal Simulation - Rth / Zth
To estimate the thermal influence of the assembly and interconnection technology and the different materials, the thermal resistance Rth / Zth was simulated using “Flow EFD” for the different devices.
A reduction of 9% - superior performance
For the calculation of Rth / Zth, detailed 3D-CAD models of the test devices were developed.
The calculated Rth values, shown in Figure 1 above, showed that the sintered device had a reduced value of approximately 9% compared to the reference device. This was due to the higher specific thermal conductivity of silver compared to the solder and the substantially thinner sinter layer compared to solder layers.
Figure 2: Simulation Rth-jc / Zth-jc
Here in Figure 2, the dotted blue curve represents the improvement (in %) of Zth of the DBB device (solid blue curve) as compared to reference device (solid red curve). The performance of the DBB device is significantly better for time periods shorter than 0.1s.
Electrical simulation static losses – reduced voltage drop
To determine the influence of the DBB technology and the Cu bond wires, the electrical resistance of the circuit was simulated by using “ANSYS Electromagnetics, Q3D Extractor 12.0”
A DC current was applied to the grey dots in Figure 3. The IGBT was represented by a body with an electrical resistance according to the electrical resistance of the IGBT at Ic_nom.
Figure 3: Electrical Simulation – Static Losses
Figure 4a: Current density - reference device
Figure 4b: Current density - DBB device
Figure 4a and 4b show the simulation results for the reference device (4a) and DBB device (4b). The red areas correspond to a high current density and the blue to a low current density. It can be seen that the current density around the bond feet is particularly affected by the thin chip metallization.
The blue area in the centre of the chip corresponds to the gate pad and therefore has low current density. Since in the reference device chip metallization consists of a layer system with a total thickness of approximately 3µm, there is only a very thin conductor sheet available for the current flow from the bond feet to the IGBT cells at the edge of the chip.
The 100mV DBB difference
Exhibit 4b shows the current density in the DBB device. In the first loop of the copper bond wires from the DBC to the right-hand side of the chip, the current density is identical to the reference device.
However, in the second loop of the copper bond wires, calculations revealed a very low current density. This is because the majority of the current flows directly from the first stitch bond feet through the bond buffer layer to the IGBT cells.
Because of the high electrical conductivity of the copper and the much larger cross-section (more than 20 times) of the bond buffer, the current density and electrical resistance is significantly reduced. This cumulative effect of reduced current density in the Bond Buffer and the copper bond wires lowers the electrical resistance, thereby reducing the forward voltage drop by 100mV.
Forward Voltage – improved energy savings
Measuring the forward voltage Vce_sat of the devices revealed 3 different curve series, which were well separated from each other, as seen in Figure 5.
Figure 5: Measurements of Forward Voltage Vf, the picture below is magnification of the red section of the left picture.
The measurements were made at 25°C and Uge = +15V. The highest electrical resistance and subsequent electrical power loss were measured at the reference device. At 200A the voltage Vce_sat of the reference device was approximately 1.7V (see Figure 5 brown line). For the device with sintered Bond Buffer and aluminum bond wires Vce_sat of 1.64V (see Figure 5 orange line) was measured. The lowest voltage Vce_sat was measured at the DBB devices with 1.6V (see Figure 5 blue line).
In Figure 5, a comparison of the measured and the simulated results are shown. The simulated values are shown in black, revealing the alignment between simulation and measurement results. It demonstrates clearly that DBB technology has a significantly lower forward voltage drop.
Summing up, tests showed that the forward voltage in DBB is reduced by 100mV in comparison to the reference device. Because of the Danfoss Bond Buffer, the current distribution over the chip is improved significantly, leading to a reduction of 60mV. The copper bond wire contributes to a reduction of another 40mV. This leads to lower losses in the module.
The breakdown voltage and switching behaviour of all test devices are equal; the high-pressure sinter process has no negative influence on the chips; there are no changes needed in the gate resistance, drivers, or any other component in the application.
The robustness against over-current of up to 4.5 times of the nominal current is not affected, so the reverse bias safe operating area can be guaranteed.
These results clearly show that a power module with DBB technology can replace any existing module, thereby giving the opportunity to increase power density without changing the system.
About Danfoss Silicon Power
Danfoss Silicon Power is the expert in design and manufacturing of power modules and stacks individually designed to meet application requirements. In addition to customer-specific solutions, we design, manufacture and market a wide selection of plug-in compatible power modules. Globally, Danfoss cover an extensive range of business areas such as consumer appliances, industrial controls and automotive, as well as medical equipment and renewable energy applications. Based in Germany, Danfoss is the supplier to some of the world’s leading companies.
- G. Mannmeusel, M. Bäßler, H. Ströbel-Maier, M. Becker, F. Osterwald; Influence of Danfoss Bond Buffer and Cu-Wire Bonds on the Electrical Switching Behaviour of IGBTs; PCIM 2014, Nürnberg
- The effects of DBB devices on improved lifetime is explained in the paper:
J. Rudzki, F. Osterwald, M. Becker, R. Eisele; Novel Cu-bond contacts on sintered metal buffer for power module with extended capabilities; PCIM 2012, Nürnberg