Zenasis Technologies Inc. (Campbell, CA) unveiled its hybrid optimization technology for high-performance integrated circuit (IC) design. Currently in limited, pre-beta use with select customers, Zenasis will introduce its products for standard-cell-based designs, based on its hybrid optimization technology, early next year.
"Physical synthesis solutions have come a long way in solving the timing closure problem between synthesis and place and route," stated Zenasis President and CEO Jay Roy. "And yet, the design still maps to small cells from a fixed library that limit design quality. This creates designs with too many cells and interconnect wires, problems we believe we can solve."