Unified Power Model for System-Level IC Design being Developed
Silicon Integration Initiative, Inc. (Si2), a research and development joint venture focused on integrated circuit design tool interoperability standards, has launched a System Level Power working group to create the Si2 Unified Power Model (UPM), a standard which will strengthen power management in system-level IC design.
Jerry Frenkil, director of the OpenStandards Coalition, which incubates new Si2 standards, said development of the Si2 UPM is part of the industry's ongoing effort to improve energy and power efficiency throughout the system-on-a-chip development flow, with a focus on system design.
"Energy efficiency is a growing and costly constraint in integrated circuit design," Frenkil explained. "There's currently no standard, single model to represent power data at the system level across a range of process, voltage, and temperature (PVT) points.
"Different, often inconsistent models are currently used in each of the three major stages of IC design: system design, register transfer level (RTL) design, and implementation. None of those models currently support voltage or temperature dependencies. The Si2 UPM addresses those issues.
"When completed, the Si2 UPM will enable faster turnaround time for system-level power and thermal analyses, as well as reduce resources and costs incurred in power model generation," Frenkil added.
The approved specification, including the capability to supply power data to IEEE 1801/UPF power state models, will be contributed to the IEEE P2416 Working Group for ongoing maintenance and industry-wide standardization. IEEE P2416 supports the ability to develop accurate, efficient and interoperable power models for complex, integrated circuit designs.
Si2 members participating in the working group are ANSYS, Cadence Design Systems, IBM, Intel and Entasys. The Si2 UPM will benefit the three major constituencies to the IC design ecosystem:
- For IP providers
- A system-level power data model companion for the IEEE 1801 (UPF) power state model
- Reduced time and resources for model and library generation and support
- For system and SoC architects
- True system-level modeling that eliminates the need for gate-level netlists
- Faster turn-around time for system-level power and thermal analyses
- Model consistency across abstractions
- For EDA providers
- New, non-cannibalistic product and solution opportunities