Consortium to address Wafer-Level Packaging Challenges

June 29, 2016 by Jeff Shepard

A*STAR's Institute of Microelectronics (IME) has partnered leading semiconductor companies to develop cost-effective solutions in 2.5D and 3D wafer-level integrated circuit (IC) packaging. The newly formed Chip-on-Wafer Consortium II and the Cost-Effective Interposer Consortium will leverage IME's expertise in 3D and 2.5D IC integration; bonding technologies; as well as the design and packaging of semiconductor dies to develop advanced chip packaging solutions. All these capabilities will lead to cost savings and high-volume manufacturing.

In today’s mobile and connected world, consumers demand next-generation devices that are multi-functional, more compact, offer better performance, and consume less power. As the industry moves towards more innovative technologies to keep pace with market trends, it must also keep manufacturing costs low to remain competitive.

The Chip-on-Wafer (CoW) Consortium II will build on the success of the first CoW consortium to further reduce production time and costs for 3D and 2.5D packaging. In the CoW Consortium I, IME and its partners successfully demonstrated Chip-on-Wafer bonding with Copper-Copper (Cu-Cu) diffusion bonding technology. The two-step process involves temporary flip-chip bonding and permanent gang bonding at a temperature of 200 degree C. This enables the scaling of the interconnect pitch of the integrated circuit from the average of 40µm to 6µm.

The consortium achieved the highest throughput bonding – five times faster than the conventional solder-assisted thermo-compression bonding technique –making the flip-chip bonding of thin (20µm) through-silicon via (TSV) dies possible without damaging the chip.

These technological breakthroughs will allow device manufacturers to better integrate 3D chipsets such as CMOS image sensors, signal processors, logic and memory, and memory stacks. They will also increase the overall throughput by 400 to 500 per cent and lower the manufacturing cost by approximately 40 per cent.

The CoW Consortium II will further develop the Cu-Cu diffusion bonding technology for energy-efficient and highly reliable devices. This technology will be applied in the development of 3D memory stack and 2.5D integration of a field-programmable gate array (FPGA) and memory on TSV-less interposer. It aims to achieve these by demonstrating a low-temperature Cu-Cu bonding with narrow-gap (3 to 5µm) flip-chip bonding, where the narrow gap is filled with optimized pre-applied under-fill.

Prior to the Cost-Effective Interposer Consortium, IME’s 2.5D Through-Silicon Interposer (TSI) Consortium successfully demonstrated an end-to-end design-process-assembly-packaging flow for large area (39mm by 27mm) TSI with dense multi-level Cu interconnects. FPGA and Dynamic Random Access Memory (DRAM) ICs were integrated for high-performance and power-efficient systems. The consortium also developed a 2.5D TSI process design kit (PDK) and electronic design automation (EDA) flow for fabless companies to design TSI, and subsequently perform wafer fabrication, assembly and packaging at IME’s 300mm wafer fabrication facility. These achievements afford companies across the value chain a lower cost of entry, and seamless design-to-manufacturing flow for 2.5D TSI technology. IME worked closely with Foundry, OSAT, Materials, Equipment, EDA, Fabless partners to capture their design and manufacturing requirements, and overcome challenges associated with the volume production of 2.5D TSI.

The Cost-Effective Interposer Consortium will address the high manufacturing costs of interposers. It will address the capability limitations in silicon interposers for FPGA and graphic processing unit (GPU) IC designs for 2.5D and 3D IC packaging. IME and its partners will integrate value-added analog and power management units to the silicon interposer and develop an interposer which will not require TSV processing; hence reducing the cost of silicon interposers by up to 50 per cent.

Prof. Dim-Lee Kwong, Executive Director of IME said, “The outstanding results of phase 1 of our past consortia bring us to a new milestone in advanced chip packaging. They will play a foundational role in meeting challenging requirements for highly integrated mobile applications and connected devices. Moving forward, I am confident that IME’s close collaboration with our partners will continue to take our advanced packaging technologies and solutions to greater heights, and spur the mass adoption of cost-effective high performance systems.”

Lena Nicolaides, Vice President and General Manager of SWIFT Division, KLA-Tencor stated: “Our strategic alliance with IME and industry partners has allowed us to tackle complicated process challenges in system design. This advances our yield management and process control strategies for production of devices with better functionality, lower cost and lower power consumption. We look forward to contributing our expertise in inspection and metrology in the Chip-on-Wafer Consortium II, and the Cost-Effective Interposer Consortium, as we further develop commercial solutions for the industry.”

Yuichi Abe, Vice-President and General Manager, Tokyo Electron Ltd., ATSBU commented, “Wafer level bonding is an emerging technology that has a huge potential to overcome various process limitations in semiconductor packaging. Our R&D collaboration with IME in wafer level bonding technology has proved to be rewarding with the successful demonstration of high throughput two-step chip-on-wafer bonding method. IME’s expertise in the packaging technology and its state-of-the-art facilities will expedite the development and time-to-market of semiconductor equipment. We look forward to developing a wide range of bonding technologies which include high accuracy fusion bonding for 3D stacking and eutectic bonding for various MEMS applications.”