Intel Looks to Improve Backside Power Delivery with new RibbonFET and PowerVia Architectures
Intel announced the company's future process and packaging technology roadmaps at its "Accelerated" webcast last week.
Improving Backside Power Delivery
PowerVia is Intel’s take on backside power delivery, designed by the manufacturer to optimize signal transmission by scrapping the need for power routing on the front side of the wafer.
The industry-first solution features optimized signal routing to reduce power leakage and utilizes NANO through-silicon via (TSV) packaging technology 500 times smaller than most competitors, to deliver substantially increased computing performance.
The new PowerVia technology. Image used courtesy of Intel.
As explained in an article on All About Circuits, backside power delivery works considerably better than conventional methods when scaling, offering a 1% voltage margin compared to the industry-standard 10%.
This technique could therefore aid Intel to scale its solutions faster, particularly since it has also been shown to significantly decrease resistance in power delivery networks.
A New Transistor Architecture
RibbonFET is Intel’s new design of a gate-all-around transistor and represents the firm’s first novel transistor architecture since its FinFET.
The technology is designed to deliver faster transistor switching speeds while retaining the same drive current as multiple fins in a smaller footprint. In addition, also with RibbonFET Intel will offer backside power delivery.
For context, current nodes utilize FinFET transistors, but the technology is quickly being replaced by RibbonFETs.
Intel’s new RibbonFET technology. Image used courtesy of Intel.
Intel's node Intel 20A will reportedly be the first one equipped with the new transistor architecture, dubbed the '2nm' process. These transistors are reportedly smaller and faster to switch, which should also lead to better performance.
Nodes up to 3nm, on the other hand, will continue to use FinFET transistors, Intel said last year.
Moving forward, the firm said RibbonFET and PowerVia will be combined. Through the novel technologies, Intel hopes to eliminate the need for power routing on the front side of the wafer.
The goal can be reportedly achieved thanks to the fact that, in these devices, the bottom layer can be used for the power supply, while the top layer for the transistors.
This, in turn, allows wafers to be designed both more efficiently and more cost-effectively.
Intel plans to use RibbonFET in its Intel 20A process by the end of 2024.
Intel’s Accelerated Webcast
During the online event, which took place on July 26, Intel CEO Pat Gelsinger, together with Dr. Ann B. Kelleher, Intel Senior Vice President of Technology Development presented a range of breakthrough technologies.
Pat Gelsinger, speaking at the Intel Accelerated event. Image used courtesy of Intel.
As mentioned above, the webcast explored Intel’s new RibbonFET and PowerVia technologies, as well as Intel’s planned adoption of next-generation extreme ultraviolet lithography (EUV).
Often referred to as High Numerical Aperture EUV, the technology will enable Intel to receive the industry’s first High NA EUV production tool.
According to the event page on the firm’s website, the new technologies will accelerate the path back to process performance leadership as well as bolstering the company’s packaging capabilities.
What do you think about Intel Accelerated and the company’s new power technologies? Let us know in the comments down below.